Simulation Results: alert_handler

 
15/07/2026 19:40:28 DVSim: v1.49.12 sha: 62fb2eb json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.38 %
  • code
  • 90.71 %
  • assert
  • 98.29 %
  • func
  • 76.15 %
  • line
  • 99.73 %
  • branch
  • 98.11 %
  • cond
  • 91.14 %
  • toggle
  • 87.15 %
  • FSM
  • 77.42 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 7.570s 83.371us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 8.340s 561.867us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 2.480s 109.634us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 211.070s 12566.300us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 42.560s 617.498us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 8.320s 628.462us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 2.480s 109.634us 1 1 100.00
alert_handler_csr_aliasing 42.560s 617.498us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 122.770s 16943.882us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 26.650s 1847.533us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1290.330s 37104.330us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 13.330s 320.928us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 7.570s 83.371us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 27.090s 1408.392us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 30.100s 1614.129us 1 1 100.00
ping_timeout 1 1 100.00
alert_handler_ping_timeout 213.170s 7335.923us 1 1 100.00
lpg 2 2 100.00
alert_handler_lpg 1341.040s 77173.341us 1 1 100.00
alert_handler_lpg_stub_clk 2137.620s 362308.201us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 1232.020s 85005.355us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 4.080s 167.841us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.410s 22.437us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.380s 11.284us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 4.500s 499.561us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 4.500s 499.561us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 8.340s 561.867us 1 1 100.00
alert_handler_csr_rw 2.480s 109.634us 1 1 100.00
alert_handler_csr_aliasing 42.560s 617.498us 1 1 100.00
alert_handler_same_csr_outstanding 9.280s 103.435us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 8.340s 561.867us 1 1 100.00
alert_handler_csr_rw 2.480s 109.634us 1 1 100.00
alert_handler_csr_aliasing 42.560s 617.498us 1 1 100.00
alert_handler_same_csr_outstanding 9.280s 103.435us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 141.750s 7626.337us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 141.750s 7626.337us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 141.750s 7626.337us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 141.750s 7626.337us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 217.160s 3759.099us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 10.970s 1022.391us 1 1 100.00
alert_handler_tl_intg_err 71.040s 17519.808us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 71.040s 17519.808us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 141.750s 7626.337us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 7.570s 83.371us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 7.570s 83.371us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 7.570s 83.371us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 7.570s 83.371us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 13.330s 320.928us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 1341.040s 77173.341us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 13.330s 320.928us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1290.330s 37104.330us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1290.330s 37104.330us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 10.970s 1022.391us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 10.970s 1022.391us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 10.970s 1022.391us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 10.970s 1022.391us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 10.970s 1022.391us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 10.970s 1022.391us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 10.970s 1022.391us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 10.970s 1022.391us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 10.970s 1022.391us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 90.950s 4016.332us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 18091724939032374177814710085752837313412198639284824507643224146478190303382 192
UVM_INFO @ 167841341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 45442351756835671244670748399391118941627113389290817073467346680842987074279 123
UVM_INFO @ 4016331871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---