Simulation Results: clkmgr

 
15/07/2026 19:40:28 DVSim: v1.49.12 sha: 62fb2eb json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 70.93 %
  • code
  • 68.71 %
  • assert
  • 89.88 %
  • func
  • 54.20 %
  • line
  • 81.66 %
  • branch
  • 86.53 %
  • cond
  • 78.85 %
  • toggle
  • 96.51 %
  • FSM
  • 0.00 %
Validation stages
V1
33.33%
V2
53.85%
V2S
25.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.150s 45.000us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.350s 88.155us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.640s 8.931us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 2.220s 129.770us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.850s 28.475us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 0.700s 8.908us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
clkmgr_csr_rw 0.640s 8.931us 0 1 0.00
clkmgr_csr_aliasing 0.850s 28.475us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.770s 25.581us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.990s 37.282us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.020s 16.829us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.150s 45.000us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.640s 11.703us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.700s 11.421us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.640s 11.703us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 0.950s 44.481us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 1.190s 23.422us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 3.390s 158.267us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 3.390s 158.267us 1 1 100.00
tl_d_outstanding_access 1 4 25.00
clkmgr_csr_hw_reset 1.350s 88.155us 1 1 100.00
clkmgr_csr_rw 0.640s 8.931us 0 1 0.00
clkmgr_csr_aliasing 0.850s 28.475us 0 1 0.00
clkmgr_same_csr_outstanding 0.870s 11.745us 0 1 0.00
tl_d_partial_access 1 4 25.00
clkmgr_csr_hw_reset 1.350s 88.155us 1 1 100.00
clkmgr_csr_rw 0.640s 8.931us 0 1 0.00
clkmgr_csr_aliasing 0.850s 28.475us 0 1 0.00
clkmgr_same_csr_outstanding 0.870s 11.745us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 1.540s 78.478us 0 1 0.00
clkmgr_tl_intg_err 0.620s 2.961us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.230s 63.896us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.230s 63.896us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.230s 63.896us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.230s 63.896us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.630s 6.843us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.620s 2.961us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.640s 11.703us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.700s 11.421us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.230s 63.896us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.160s 60.420us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.640s 8.931us 0 1 0.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 1.540s 78.478us 0 1 0.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.640s 8.931us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.640s 8.931us 0 1 0.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 1.540s 78.478us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.750s 8.209us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 0.680s 9.503us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 3 test runs
clkmgr_frequency_timeout 49061760046990782918561227932838876340313506926692601786674606168155898416278 78
UVM_INFO @ 11420661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 79483171953872670391942674748450062201773819349432422765908284430618379704756 79
UVM_INFO @ 9502664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 107153681467627895330656529575049411240948013541846369741512544238840641428853 81
UVM_INFO @ 44480650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 3 test runs
clkmgr_tl_intg_err 11748704003193595183310356051397640290624829669790175336253654290044871381393 75
UVM_INFO @ 2961472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_aliasing 65901995714016956760992559845243540771842291866418247334713966054726433950001 75
UVM_INFO @ 28474754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 65742819080726488607363379739822302396774559976849639630836069534865894731975 76
UVM_INFO @ 8908096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 2 test runs
clkmgr_shadow_reg_errors_with_csr_rw 84855517104888397499289107289757474254645827373839637824869159311850764206452 75
UVM_INFO @ 6842983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 59174145443036354155119078594819524876535334291558887106475846815291562342694 75
UVM_INFO @ 8931214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 1 test run
clkmgr_frequency 85087393874143901864126756926280557722472567184946061904742276533303342485213 78
UVM_INFO @ 11703208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed 1 test run
clkmgr_regwen 55761842728458114354440178497907622208144737533759706588363599306654833873207 74
UVM_INFO @ 8208958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 91937771046265150543301879647468198480875270499699235419043421611039022335444 142
UVM_INFO @ 78478417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 84965741629772014491162622708632116648511995309976988193832370669484170632333 75
UVM_INFO @ 129770278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 10064728536077288225272802371535476483352729221096969059964882018358871759111 75
UVM_INFO @ 11745037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---