Simulation Results: csrng

 
15/07/2026 19:40:28 DVSim: v1.49.12 sha: 62fb2eb json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 76.27 %
  • code
  • 88.91 %
  • assert
  • 93.01 %
  • func
  • 46.89 %
  • block
  • 95.21 %
  • line
  • 95.88 %
  • branch
  • 88.39 %
  • toggle
  • 85.67 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 16.358us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 48.016us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 67.765us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 22.000s 793.488us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 2.000s 82.321us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 36.062us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 67.765us 1 1 100.00
csrng_csr_aliasing 2.000s 82.321us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 3.000s 48.631us 1 1 100.00
alerts 1 1 100.00
csrng_alert 8.000s 185.797us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 20.254us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 2.000s 18.150us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 2.000s 18.150us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 9.000s 180.953us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 34.517us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 44.041us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 2.000s 75.756us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 2.000s 75.756us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 48.016us 1 1 100.00
csrng_csr_rw 2.000s 67.765us 1 1 100.00
csrng_csr_aliasing 2.000s 82.321us 1 1 100.00
csrng_same_csr_outstanding 2.000s 32.657us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 48.016us 1 1 100.00
csrng_csr_rw 2.000s 67.765us 1 1 100.00
csrng_csr_aliasing 2.000s 82.321us 1 1 100.00
csrng_same_csr_outstanding 2.000s 32.657us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 3.000s 155.796us 1 1 100.00
csrng_tl_intg_err 3.000s 129.574us 1 1 100.00
sec_cm_config_regwen 1 2 50.00
csrng_regwen 2.000s 3.115us 0 1 0.00
csrng_csr_rw 2.000s 67.765us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 8.000s 185.797us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 9.000s 180.953us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 3.000s 48.631us 1 1 100.00
csrng_err 2.000s 20.254us 1 1 100.00
csrng_sec_cm 3.000s 155.796us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 3.000s 48.631us 1 1 100.00
csrng_err 2.000s 20.254us 1 1 100.00
csrng_sec_cm 3.000s 155.796us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 3.000s 48.631us 1 1 100.00
csrng_err 2.000s 20.254us 1 1 100.00
csrng_sec_cm 3.000s 155.796us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 3.000s 48.631us 1 1 100.00
csrng_err 2.000s 20.254us 1 1 100.00
csrng_sec_cm 3.000s 155.796us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 3.000s 48.631us 1 1 100.00
csrng_err 2.000s 20.254us 1 1 100.00
csrng_sec_cm 3.000s 155.796us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 8.000s 185.797us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 3.000s 48.631us 1 1 100.00
csrng_err 2.000s 20.254us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 9.000s 180.953us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 8.000s 185.797us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 3.000s 129.574us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 3.000s 48.631us 1 1 100.00
csrng_err 2.000s 20.254us 1 1 100.00
csrng_sec_cm 3.000s 155.796us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 3.000s 48.631us 1 1 100.00
csrng_err 2.000s 20.254us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 3.000s 48.631us 1 1 100.00
csrng_err 2.000s 20.254us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 3.000s 48.631us 1 1 100.00
csrng_err 2.000s 20.254us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 3.000s 48.631us 1 1 100.00
csrng_err 2.000s 20.254us 1 1 100.00
csrng_sec_cm 3.000s 155.796us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 3.000s 48.631us 1 1 100.00
csrng_err 2.000s 20.254us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 3602.052s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 82949537787800750298479607550067891201802514901152961808086049165072372465046 100
UVM_INFO @ 18150477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:67) virtual_sequencer [csrng_regwen_vseq] Was unable to flip INT_STATE_READ_ENABLE 1 test run
csrng_regwen 5754456858490390544583533557832674947235763256906712765796722683117237659497 99
UVM_INFO @ 3114783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 12397266922673132095811373122018003976129000993624747175896773462922207138981 None