Simulation Results: dma

 
15/07/2026 19:40:28 DVSim: v1.49.12 sha: 62fb2eb json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.58 %
  • code
  • 90.38 %
  • assert
  • 96.61 %
  • func
  • 60.76 %
  • block
  • 97.34 %
  • line
  • 96.85 %
  • branch
  • 95.76 %
  • toggle
  • 77.37 %
  • FSM
  • 91.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 4.000s 777.446us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 5.000s 315.013us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 9.000s 4328.601us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 19.509us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 7.000s 41.756us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 10.000s 444.070us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 4.000s 580.003us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 25.087us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 7.000s 41.756us 1 1 100.00
dma_csr_aliasing 4.000s 580.003us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 26.000s 4268.951us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 360.000s 156758.286us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 291.000s 114410.017us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 291.000s 114410.017us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 360.000s 156758.286us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 300.000s 109787.934us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 291.000s 114410.017us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 8.000s 663.862us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 37.000s 13194.947us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 12.765us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 12.397us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 3.000s 1147.073us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 3.000s 1147.073us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 19.509us 1 1 100.00
dma_csr_rw 7.000s 41.756us 1 1 100.00
dma_csr_aliasing 4.000s 580.003us 1 1 100.00
dma_same_csr_outstanding 2.000s 44.056us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 19.509us 1 1 100.00
dma_csr_rw 7.000s 41.756us 1 1 100.00
dma_csr_aliasing 4.000s 580.003us 1 1 100.00
dma_same_csr_outstanding 2.000s 44.056us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 9.000s 543.684us 1 1 100.00
dma_generic_stress 300.000s 109787.934us 1 1 100.00
dma_handshake_stress 291.000s 114410.017us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 7.000s 316.875us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 2.000s 421.719us 1 1 100.00
dma_sec_cm 1.000s 9.917us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 107.000s 7190.117us 1 1 100.00
dma_longer_transfer 5.000s 226.133us 1 1 100.00
dma_stress_all_with_rand_reset 2.000s 444.670us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1287) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 22663230517120933142428848868679859807190521865168203164988843615693694965939 91
UVM_INFO @ 444669933ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---