Simulation Results: edn/edn1

 
15/07/2026 19:40:28 DVSim: v1.49.12 sha: 62fb2eb json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.34 %
  • code
  • 83.17 %
  • assert
  • 98.18 %
  • func
  • 80.67 %
  • line
  • 97.95 %
  • branch
  • 93.07 %
  • cond
  • 90.31 %
  • toggle
  • 94.74 %
  • FSM
  • 39.77 %
Validation stages
V1
100.00%
V2
92.86%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.820s 50.919us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.730s 27.235us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.710s 86.799us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.520s 140.637us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.280s 78.629us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.030s 245.997us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.710s 86.799us 1 1 100.00
edn_csr_aliasing 1.280s 78.629us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 4.290s 867.287us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 4.290s 867.287us 1 1 100.00
genbits 1 1 100.00
edn_genbits 4.290s 867.287us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.790s 40.771us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.910s 22.976us 1 1 100.00
errs 1 1 100.00
edn_err 1.440s 28.414us 1 1 100.00
disable 1 2 50.00
edn_disable 1.110s 12.623us 1 1 100.00
edn_disable_auto_req_mode 11.430s 500.000us 0 1 0.00
stress_all 1 1 100.00
edn_stress_all 1.720s 432.167us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.720s 20.006us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.770s 44.417us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.420s 106.987us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.420s 106.987us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.730s 27.235us 1 1 100.00
edn_csr_rw 0.710s 86.799us 1 1 100.00
edn_csr_aliasing 1.280s 78.629us 1 1 100.00
edn_same_csr_outstanding 0.880s 189.291us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.730s 27.235us 1 1 100.00
edn_csr_rw 0.710s 86.799us 1 1 100.00
edn_csr_aliasing 1.280s 78.629us 1 1 100.00
edn_same_csr_outstanding 0.880s 189.291us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.460s 496.684us 1 1 100.00
edn_tl_intg_err 1.800s 96.320us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.840s 18.949us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.910s 22.976us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.460s 496.684us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.460s 496.684us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.460s 496.684us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.460s 496.684us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.910s 22.976us 1 1 100.00
edn_sec_cm 3.460s 496.684us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.910s 22.976us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.800s 96.320us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 60.370s 16093.666us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
edn_disable_auto_req_mode 38833135640586799605443929286281648972604225572725789345628024519965537320506 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---