Simulation Results: entropy_src/rng_16bits

 
15/07/2026 19:40:28 DVSim: v1.49.12 sha: 62fb2eb json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 66.96 %
  • code
  • 79.02 %
  • assert
  • 73.78 %
  • func
  • 48.08 %
  • block
  • 93.65 %
  • line
  • 97.32 %
  • branch
  • 85.10 %
  • toggle
  • 52.43 %
  • FSM
  • 81.25 %
Validation stages
V1
83.33%
V2
93.75%
V2S
85.71%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 2.000s 59.301us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 76.157us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 1.000s 85.254us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 14.000s 1603.426us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 5.000s 832.869us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 6.000s 7.625us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 1.000s 85.254us 1 1 100.00
entropy_src_csr_aliasing 5.000s 832.869us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 2 3 66.67
entropy_src_smoke 2.000s 59.301us 1 1 100.00
entropy_src_rng 56.000s 13230.616us 1 1 100.00
entropy_src_fw_ov 92.000s 3661.664us 0 1 0.00
firmware_mode 0 1 0.00
entropy_src_fw_ov 92.000s 3661.664us 0 1 0.00
rng_mode 1 1 100.00
entropy_src_rng 56.000s 13230.616us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 108.000s 13161.507us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 56.000s 13230.616us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 56.000s 13230.616us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 56.000s 13230.616us 1 1 100.00
entropy_src_intr 15.000s 363.884us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 56.000s 13230.616us 1 1 100.00
entropy_src_functional_alerts 5.000s 1540.779us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 103.000s 14221.359us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 2.000s 187.611us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 2.000s 131.463us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 1.000s 59.034us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 21.811us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 3.000s 67.861us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 3.000s 67.861us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 76.157us 1 1 100.00
entropy_src_csr_rw 1.000s 85.254us 1 1 100.00
entropy_src_csr_aliasing 5.000s 832.869us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 25.970us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 76.157us 1 1 100.00
entropy_src_csr_rw 1.000s 85.254us 1 1 100.00
entropy_src_csr_aliasing 5.000s 832.869us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 25.970us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 2.000s 314.241us 1 1 100.00
entropy_src_tl_intg_err 2.000s 68.922us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 56.000s 13230.616us 1 1 100.00
entropy_src_cfg_regwen 2.000s 20.776us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 56.000s 13230.616us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 56.000s 13230.616us 1 1 100.00
sec_cm_intersig_mubi 1 2 50.00
entropy_src_rng 56.000s 13230.616us 1 1 100.00
entropy_src_fw_ov 92.000s 3661.664us 0 1 0.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 187.611us 1 1 100.00
entropy_src_sec_cm 2.000s 314.241us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 187.611us 1 1 100.00
entropy_src_sec_cm 2.000s 314.241us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 56.000s 13230.616us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 187.611us 1 1 100.00
entropy_src_sec_cm 2.000s 314.241us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 187.611us 1 1 100.00
entropy_src_sec_cm 2.000s 314.241us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 2.000s 187.611us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 5.000s 1540.779us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 2.000s 68.922us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 157.000s 13075.490us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 12.000s 5721.769us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1663) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.alert_test 1 test run
entropy_src_stress_all_with_rand_reset 99163644046035806637082760106413428443243631710152624906577607015370732791348 120
UVM_INFO @ 5721769097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:268) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_alert triggered unexpectedly 1 test run
entropy_src_fw_ov 114545119961026542168424763719640883856383016735582048684286664362153631606538 797
UVM_INFO @ 3661663702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror alert_fail_counts 1 test run
entropy_src_csr_mem_rw_with_rand_reset 63534585247535154487949160530345415010550883294633631337926900239892902747334 113
UVM_INFO @ 7624860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---