Simulation Results: hmac

 
15/07/2026 19:40:28 DVSim: v1.49.12 sha: 62fb2eb json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 74.23 %
  • code
  • 95.95 %
  • assert
  • 97.17 %
  • func
  • 29.56 %
  • block
  • 97.46 %
  • line
  • 98.39 %
  • branch
  • 93.64 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 14.000s 2836.205us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 2.000s 33.959us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 1.000s 42.939us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 8.000s 321.641us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 6.000s 993.880us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 382.000s 42724.131us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 1.000s 42.939us 1 1 100.00
hmac_csr_aliasing 6.000s 993.880us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 101.000s 10117.314us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 12.000s 636.423us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 10.000s 943.593us 1 1 100.00
hmac_test_sha384_vectors 22.000s 643.189us 1 1 100.00
hmac_test_sha512_vectors 409.000s 16302.368us 1 1 100.00
hmac_test_hmac256_vectors 11.000s 1317.860us 1 1 100.00
hmac_test_hmac384_vectors 14.000s 1724.437us 1 1 100.00
hmac_test_hmac512_vectors 18.000s 5275.019us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 2.000s 28.670us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 66.000s 7954.211us 1 1 100.00
error 1 1 100.00
hmac_error 60.000s 7286.937us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 105.000s 26738.264us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 14.000s 2836.205us 1 1 100.00
hmac_long_msg 101.000s 10117.314us 1 1 100.00
hmac_back_pressure 12.000s 636.423us 1 1 100.00
hmac_datapath_stress 66.000s 7954.211us 1 1 100.00
hmac_burst_wr 2.000s 28.670us 1 1 100.00
hmac_stress_all 294.000s 115899.346us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 14.000s 2836.205us 1 1 100.00
hmac_long_msg 101.000s 10117.314us 1 1 100.00
hmac_back_pressure 12.000s 636.423us 1 1 100.00
hmac_datapath_stress 66.000s 7954.211us 1 1 100.00
hmac_wipe_secret 105.000s 26738.264us 1 1 100.00
hmac_test_sha256_vectors 10.000s 943.593us 1 1 100.00
hmac_test_sha384_vectors 22.000s 643.189us 1 1 100.00
hmac_test_sha512_vectors 409.000s 16302.368us 1 1 100.00
hmac_test_hmac256_vectors 11.000s 1317.860us 1 1 100.00
hmac_test_hmac384_vectors 14.000s 1724.437us 1 1 100.00
hmac_test_hmac512_vectors 18.000s 5275.019us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 14.000s 2836.205us 1 1 100.00
hmac_long_msg 101.000s 10117.314us 1 1 100.00
hmac_back_pressure 12.000s 636.423us 1 1 100.00
hmac_datapath_stress 66.000s 7954.211us 1 1 100.00
hmac_burst_wr 2.000s 28.670us 1 1 100.00
hmac_error 60.000s 7286.937us 1 1 100.00
hmac_wipe_secret 105.000s 26738.264us 1 1 100.00
hmac_test_sha256_vectors 10.000s 943.593us 1 1 100.00
hmac_test_sha384_vectors 22.000s 643.189us 1 1 100.00
hmac_test_sha512_vectors 409.000s 16302.368us 1 1 100.00
hmac_test_hmac256_vectors 11.000s 1317.860us 1 1 100.00
hmac_test_hmac384_vectors 14.000s 1724.437us 1 1 100.00
hmac_test_hmac512_vectors 18.000s 5275.019us 1 1 100.00
hmac_stress_all 294.000s 115899.346us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 294.000s 115899.346us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 2.000s 17.081us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 6.000s 95.842us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.000s 31.771us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.000s 31.771us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 2.000s 33.959us 1 1 100.00
hmac_csr_rw 1.000s 42.939us 1 1 100.00
hmac_csr_aliasing 6.000s 993.880us 1 1 100.00
hmac_same_csr_outstanding 3.000s 315.283us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 2.000s 33.959us 1 1 100.00
hmac_csr_rw 1.000s 42.939us 1 1 100.00
hmac_csr_aliasing 6.000s 993.880us 1 1 100.00
hmac_same_csr_outstanding 3.000s 315.283us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.000s 137.505us 1 1 100.00
hmac_tl_intg_err 3.000s 781.390us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.000s 781.390us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 14.000s 2836.205us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.000s 143.589us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 57.000s 5018.764us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 3.000s 205.169us 1 1 100.00