Simulation Results

Simulation Results: i2c

15/07/2026 19:40:28 DVSim: v1.49.12 sha: 62fb2eb json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
88.53 %

code
89.11 %

assert
96.41 %

func
80.07 %

block
95.87 %

line
95.32 %

branch
92.58 %

toggle
86.53 %

FSM
82.01 %

Validation stages

V1		100.00%
V2		82.93%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	37.000s	5588.028us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	19.000s	1112.771us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	7.000s	22.427us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	2.000s	20.524us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	5.000s	2228.507us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	2.000s	139.048us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	2.000s	73.841us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	2.000s	20.524us	1	1	100.00
	i2c_csr_aliasing	2.000s	139.048us	1	1	100.00

34/41 passed

82.93 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	6.000s	420.992us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	3600.000s	0.000us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	14.000s	5926.896us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	1.000s	15.720us	1	1	100.00
host_fifo_watermark				0	1	0.00
	i2c_host_fifo_watermark	3601.000s	0.000us	0	1	0.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	1216.000s	1690.830us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	2.000s	984.002us	1	1	100.00
	i2c_host_fifo_fmt_empty	17.000s	402.819us	1	1	100.00
	i2c_host_fifo_reset_rx	5.000s	356.843us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	72.000s	1934.908us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	28.000s	1656.260us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	1.000s	4.361us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	4.000s	908.392us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	25.000s	63141.639us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	5.000s	1540.259us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	20.000s	5474.458us	1	1	100.00
	i2c_target_intr_smoke	6.000s	1091.610us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	2.000s	458.051us	1	1	100.00
	i2c_target_fifo_reset_tx	1.000s	228.836us	1	1	100.00
target_fifo_full				2	3	66.67
	i2c_target_stress_wr	10.000s	13710.251us	1	1	100.00
	i2c_target_stress_rd	20.000s	5474.458us	1	1	100.00
	i2c_target_intr_stress_wr	3600.000s	0.000us	0	1	0.00
target_timeout				1	1	100.00
	i2c_target_timeout	7.000s	3258.372us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	273.000s	1566.740us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	7.000s	942.188us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	30.000s	10094.368us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	4.000s	608.210us	1	1	100.00
	i2c_target_fifo_watermarks_tx	3.000s	620.703us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	14.000s	5926.896us	1	1	100.00
	i2c_host_perf_precise	3.000s	307.444us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	28.000s	1656.260us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	3.000s	263.468us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	4.000s	549.633us	1	1	100.00
	i2c_target_nack_acqfull_addr	9.000s	858.464us	1	1	100.00
	i2c_target_nack_txstretch	3.000s	502.584us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	5.000s	736.669us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	3.000s	993.392us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	1.000s	60.376us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	1.000s	18.709us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	2.000s	143.563us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	2.000s	143.563us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	7.000s	22.427us	1	1	100.00
	i2c_csr_rw	2.000s	20.524us	1	1	100.00
	i2c_csr_aliasing	2.000s	139.048us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	118.392us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	7.000s	22.427us	1	1	100.00
	i2c_csr_rw	2.000s	20.524us	1	1	100.00
	i2c_csr_aliasing	2.000s	139.048us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	118.392us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	2.000s	286.347us	1	1	100.00
	i2c_sec_cm	2.000s	95.551us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	2.000s	286.347us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	5.000s	187.754us	1
target_error_intr				1
	i2c_target_unexp_stop	1.000s	38.637us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	3.000s	420.716us	1

Error Messages

	Test	seed	line	log context
Job timed out after * minutes				3 test runs
	i2c_host_fifo_watermark	15197986276865807685851692386602622477978238817348278054724325597310727047411	None
	i2c_host_stress_all	63670119578716326827100862878964977970490942865146617873801535907487811296477	None
	i2c_target_intr_stress_wr	62232530209448864524347624816290628611720514835450227363410439479601196593867	None
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_error_intr	44191371592991266932956210294662563344094976165334924772636237424872910176119	145	UVM_INFO @ 420992391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_mode_toggle	27446084347522531399268104433167024191347894859373390068002647949231274705991	90	UVM_INFO @ 4361045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	101154724453129967902001544020009565679117479470799286317501715520130790242735	93	UVM_INFO @ 187753626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	52850375748043091947416541218005886460198802716115020390004239675075571295998	92	UVM_INFO @ 420716157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	106254048314342328111064215535502350543115194045789168403420823832102525891007	93	UVM_INFO @ 908392161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	55801934847665973617092522811797333001699108270561774128894295410874651680987	87	UVM_INFO @ 38637012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	59523824740933043129290733167834704532009643413979328778305833447104501649171	88	UVM_INFO @ 10094367688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---