Simulation Results: kmac/masked

 
15/07/2026 19:40:28 DVSim: v1.49.12 sha: 62fb2eb json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.34 %
  • code
  • 69.09 %
  • assert
  • 96.91 %
  • func
  • 78.01 %
  • line
  • 95.49 %
  • branch
  • 89.63 %
  • cond
  • 85.40 %
  • toggle
  • 29.37 %
  • FSM
  • 45.57 %
Validation stages
V1
100.00%
V2
72.41%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 66.970s 16163.876us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 0.960s 64.109us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 1.010s 29.218us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 17.730s 3161.498us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 5.710s 4322.423us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.880s 86.601us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 1.010s 29.218us 1 1 100.00
kmac_csr_aliasing 5.710s 4322.423us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.930s 13.236us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.170s 22.818us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 2696.540s 420797.218us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 247.730s 16693.026us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 27.080s 1393.944us 1 1 100.00
kmac_test_vectors_sha3_256 27.620s 9858.565us 1 1 100.00
kmac_test_vectors_sha3_384 20.970s 4419.987us 1 1 100.00
kmac_test_vectors_sha3_512 864.730s 28123.339us 1 1 100.00
kmac_test_vectors_shake_128 128.250s 8797.778us 1 1 100.00
kmac_test_vectors_shake_256 331.680s 88591.590us 1 1 100.00
kmac_test_vectors_kmac 3.340s 202.393us 1 1 100.00
kmac_test_vectors_kmac_xof 2.450s 63.732us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 91.010s 9652.091us 1 1 100.00
app 0 1 0.00
kmac_app 1.080s 36.933us 0 1 0.00
app_with_partial_data 0 1 0.00
kmac_app_with_partial_data 1.950s 110.289us 0 1 0.00
entropy_refresh 0 1 0.00
kmac_entropy_refresh 1.300s 103.997us 0 1 0.00
error 0 1 0.00
kmac_error 44.410s 9747.289us 0 1 0.00
key_error 0 1 0.00
kmac_key_error 0.850s 20.827us 0 1 0.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 1.210s 31.995us 0 1 0.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 1.270s 29.649us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 1.070s 23.298us 1 1 100.00
entropy_ready_error 0 1 0.00
kmac_entropy_ready_error 0.950s 17.521us 0 1 0.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.460s 24.173us 1 1 100.00
stress_all 0 1 0.00
kmac_stress_all 3.300s 265.439us 0 1 0.00
intr_test 1 1 100.00
kmac_intr_test 1.010s 69.354us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 1.150s 80.049us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 2.510s 220.228us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 2.510s 220.228us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 0.960s 64.109us 1 1 100.00
kmac_csr_rw 1.010s 29.218us 1 1 100.00
kmac_csr_aliasing 5.710s 4322.423us 1 1 100.00
kmac_same_csr_outstanding 1.820s 280.225us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 0.960s 64.109us 1 1 100.00
kmac_csr_rw 1.010s 29.218us 1 1 100.00
kmac_csr_aliasing 5.710s 4322.423us 1 1 100.00
kmac_same_csr_outstanding 1.820s 280.225us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.800s 84.748us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.800s 84.748us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.800s 84.748us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.800s 84.748us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 2.010s 51.248us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 66.210s 6275.362us 1 1 100.00
kmac_tl_intg_err 3.410s 209.133us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 3.410s 209.133us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.460s 24.173us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 66.970s 16163.876us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 91.010s 9652.091us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.800s 84.748us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 66.210s 6275.362us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 66.210s 6275.362us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 66.210s 6275.362us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 66.970s 16163.876us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.460s 24.173us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 66.210s 6275.362us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 0 1 0.00
kmac_mubi 1.050s 209.168us 0 1 0.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 66.970s 16163.876us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 7.790s 2773.002us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (kmac_scoreboard.sv:1671) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] 6 test runs
kmac_sideload_invalid 44668807530322062628654943520674102371026880349473239907303674516255814252651 76
UVM_INFO @ 31994699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_app 20666121000828880713202262308115085716805392646134346917588312171198387321868 77
UVM_INFO @ 36933310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_app_with_partial_data 62641206619476846794247363771914773210464468548311764667464868058864623164556 78
UVM_INFO @ 110289089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_refresh 91881354637626290312182452450437804978223203688198251347520483266293895338936 77
UVM_INFO @ 103997027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_error 41641851430587817883502867903793255666775816467330892989986551752708306214588 95
UVM_INFO @ 9747289029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 91230656808817745330614716562998000208239334924211030785195527092126237715090 81
UVM_INFO @ 265438668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:557) [scoreboard] Check failed (kmac_app_rsp.error == app_intf_err) 2 test runs
kmac_mubi 17793549087594859962594754701643761593363393177180931628605744712018616671133 77
UVM_INFO @ 209168471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 18011515114184514749783280553284937798815092164542639593420997325132799845106 139
UVM_INFO @ 2773002126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!$isunknown(rspfifo_rdata)) -> (!$isunknown(tl_o)))' 2 test runs
kmac_key_error 75056530514943107705584547093932259025867307112732554269750434271042998999584 78
UVM_ERROR @ 20827333 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 20827333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_ready_error 18605850594033108091670163759178545951835438284353238882339609728803548759327 78
UVM_ERROR @ 17521074 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 17521074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---