Simulation Results: lc_ctrl/volatile_unlock_disabled

 
15/07/2026 19:40:28 DVSim: v1.49.12 sha: 62fb2eb json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.72 %
  • code
  • 92.01 %
  • assert
  • 96.83 %
  • func
  • 86.31 %
  • block
  • 96.57 %
  • line
  • 97.29 %
  • branch
  • 91.26 %
  • toggle
  • 84.26 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 3.000s 858.395us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 56.558us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 89.127us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 3.000s 220.677us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 50.649us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 3.000s 18.013us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 89.127us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 50.649us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.000s 280.986us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 11.000s 350.720us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 13.315us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.000s 72.142us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 5.000s 1404.251us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.000s 438.134us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 5.000s 1404.251us 1 1 100.00
lc_ctrl_prog_failure 3.000s 72.142us 1 1 100.00
lc_ctrl_errors 7.000s 438.134us 1 1 100.00
lc_ctrl_security_escalation 6.000s 1002.895us 1 1 100.00
lc_ctrl_jtag_state_failure 26.000s 1478.259us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.000s 1956.741us 1 1 100.00
lc_ctrl_jtag_errors 56.000s 4082.790us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.000s 615.895us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.000s 630.306us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.000s 1956.741us 1 1 100.00
lc_ctrl_jtag_errors 56.000s 4082.790us 1 1 100.00
lc_ctrl_jtag_access 8.000s 4013.148us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 18.000s 2180.514us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 5.000s 105.640us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 207.498us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 10.000s 15721.184us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.000s 247.950us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 29.825us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.000s 96.047us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 139.064us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.000s 546.068us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 24.890us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 28.000s 2202.915us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.000s 18.488us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 265.150us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 265.150us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 56.558us 1 1 100.00
lc_ctrl_csr_rw 1.000s 89.127us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 50.649us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 91.680us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 56.558us 1 1 100.00
lc_ctrl_csr_rw 1.000s 89.127us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 50.649us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 91.680us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 121.138us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 48.593us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 48.593us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 11.000s 350.720us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 1404.251us 1 1 100.00
lc_ctrl_sec_cm 3.000s 121.138us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 1404.251us 1 1 100.00
lc_ctrl_sec_cm 3.000s 121.138us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.000s 1404.251us 1 1 100.00
lc_ctrl_sec_cm 3.000s 121.138us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.000s 1404.251us 1 1 100.00
lc_ctrl_sec_cm 3.000s 121.138us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 1404.251us 1 1 100.00
lc_ctrl_sec_cm 3.000s 121.138us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 1404.251us 1 1 100.00
lc_ctrl_sec_cm 3.000s 121.138us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 1404.251us 1 1 100.00
lc_ctrl_sec_cm 3.000s 121.138us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 5.000s 1404.251us 1 1 100.00
lc_ctrl_sec_cm 3.000s 121.138us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.000s 1002.895us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.000s 280.986us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.000s 630.306us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 1666.509us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 1666.509us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.000s 403.518us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 8.000s 1539.799us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 8.000s 1539.799us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3.000s 223.999us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 106857682774577892735865837254247863909704185118495890041755963770996070342608 539
UVM_INFO @ 223998664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---