Simulation Results: lc_ctrl/volatile_unlock_enabled

 
15/07/2026 19:40:28 DVSim: v1.49.12 sha: 62fb2eb json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.94 %
  • code
  • 93.68 %
  • assert
  • 95.82 %
  • func
  • 86.31 %
  • block
  • 97.07 %
  • line
  • 97.63 %
  • branch
  • 92.56 %
  • toggle
  • 86.91 %
  • FSM
  • 97.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 3.000s 55.150us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 41.923us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 111.598us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 3.000s 1814.442us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 24.789us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 266.914us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 111.598us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 24.789us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.000s 57.680us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.000s 536.200us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 22.490us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 5.000s 117.122us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.000s 288.061us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 8.000s 388.642us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.000s 288.061us 1 1 100.00
lc_ctrl_prog_failure 5.000s 117.122us 1 1 100.00
lc_ctrl_errors 8.000s 388.642us 1 1 100.00
lc_ctrl_security_escalation 6.000s 1106.241us 1 1 100.00
lc_ctrl_jtag_state_failure 29.000s 1563.964us 1 1 100.00
lc_ctrl_jtag_prog_failure 7.000s 3749.766us 1 1 100.00
lc_ctrl_jtag_errors 43.000s 2941.918us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 4.000s 382.459us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.000s 630.399us 1 1 100.00
lc_ctrl_jtag_prog_failure 7.000s 3749.766us 1 1 100.00
lc_ctrl_jtag_errors 43.000s 2941.918us 1 1 100.00
lc_ctrl_jtag_access 4.000s 394.319us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 11.000s 4135.528us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 58.712us 1 1 100.00
lc_ctrl_jtag_csr_rw 3.000s 260.781us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 17.000s 1060.184us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 8.000s 398.497us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 17.668us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.000s 111.288us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 31.576us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.000s 477.153us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 7.000s 46.492us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 12.000s 1953.881us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.000s 20.555us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 33.599us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 33.599us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 41.923us 1 1 100.00
lc_ctrl_csr_rw 1.000s 111.598us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 24.789us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 78.488us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 41.923us 1 1 100.00
lc_ctrl_csr_rw 1.000s 111.598us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 24.789us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 78.488us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 4.000s 491.653us 1 1 100.00
lc_ctrl_tl_intg_err 4.000s 135.046us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 4.000s 135.046us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.000s 536.200us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 288.061us 1 1 100.00
lc_ctrl_sec_cm 4.000s 491.653us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 288.061us 1 1 100.00
lc_ctrl_sec_cm 4.000s 491.653us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.000s 288.061us 1 1 100.00
lc_ctrl_sec_cm 4.000s 491.653us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.000s 288.061us 1 1 100.00
lc_ctrl_sec_cm 4.000s 491.653us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 288.061us 1 1 100.00
lc_ctrl_sec_cm 4.000s 491.653us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 288.061us 1 1 100.00
lc_ctrl_sec_cm 4.000s 491.653us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 288.061us 1 1 100.00
lc_ctrl_sec_cm 4.000s 491.653us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.000s 288.061us 1 1 100.00
lc_ctrl_sec_cm 4.000s 491.653us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.000s 1106.241us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.000s 57.680us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.000s 630.399us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.000s 494.552us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.000s 494.552us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.000s 206.298us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 304.813us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 304.813us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 23.000s 8475.627us 1 1 100.00