| V1 |
|
100.00% |
| V2 |
|
81.82% |
| V2S |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mbx_smoke | 1 | 1 | 100.00 | |||
| mbx_smoke | 44.000s | 4150.959us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| mbx_csr_hw_reset | 1.000s | 19.302us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| mbx_csr_rw | 6.000s | 13.953us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| mbx_csr_bit_bash | 2.000s | 105.721us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| mbx_csr_aliasing | 1.000s | 31.330us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| mbx_csr_mem_rw_with_rand_reset | 1.000s | 47.716us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| mbx_csr_rw | 6.000s | 13.953us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 1.000s | 31.330us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mbx_stress | 1 | 1 | 100.00 | |||
| mbx_stress | 99.000s | 12561.728us | 1 | 1 | 100.00 | |
| mbx_max_activity | 1 | 1 | 100.00 | |||
| mbx_stress_zero_delays | 48.000s | 2682.723us | 1 | 1 | 100.00 | |
| mbx_imbx_oob | 0 | 1 | 0.00 | |||
| mbx_imbx_oob | 2.000s | 98.177us | 0 | 1 | 0.00 | |
| mbx_doe_intr_msg | 1 | 1 | 100.00 | |||
| mbx_doe_intr_msg | 24.000s | 1503.965us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| mbx_alert_test | 2.000s | 18.322us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| mbx_intr_test | 2.000s | 38.871us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| mbx_tl_errors | 2.000s | 40.496us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| mbx_tl_errors | 2.000s | 40.496us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| mbx_csr_hw_reset | 1.000s | 19.302us | 1 | 1 | 100.00 | |
| mbx_csr_rw | 6.000s | 13.953us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 1.000s | 31.330us | 1 | 1 | 100.00 | |
| mbx_same_csr_outstanding | 2.000s | 420.785us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| mbx_csr_hw_reset | 1.000s | 19.302us | 1 | 1 | 100.00 | |
| mbx_csr_rw | 6.000s | 13.953us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 1.000s | 31.330us | 1 | 1 | 100.00 | |
| mbx_same_csr_outstanding | 2.000s | 420.785us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| mbx_tl_intg_err | 2.000s | 166.181us | 1 | 1 | 100.00 | |
| mbx_sec_cm | 1.000s | 36.603us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register | 1 test run | |||
| mbx_imbx_oob | 96195725640732463110064718299967842279453606450104425288700513334656502918176 | 94 |
UVM_INFO @ 98177464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). | 1 test run | |||
| mbx_tl_errors | 6728736400912917710216204172443036348909830306959817576505431838969955168810 | 85 |
TL item was: req: (cip_tl_seq_item@19376) { a_addr: 'h97ecbf90 a_data: 'h302d08a5 a_mask: 'h2 a_size: 'h1 a_param: 'h0 a_source: 'h7b a_opcode: 'h1 a_user: 'h25474 d_param: 'h0 d_source: 'h7b d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h10aa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 40496404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|