Simulation Results: otbn

 
15/07/2026 19:40:28 DVSim: v1.49.12 sha: 62fb2eb json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.12 %
  • code
  • 85.97 %
  • assert
  • 90.35 %
  • func
  • 97.03 %
  • block
  • 99.27 %
  • line
  • 99.47 %
  • branch
  • 94.70 %
  • toggle
  • 83.53 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 10.000s 144.298us 1 1 100.00
single_binary 1 1 100.00
otbn_single 8.000s 36.496us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 6.000s 22.032us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 4.000s 49.986us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 9.000s 177.373us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 5.000s 43.023us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 8.000s 40.930us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 4.000s 49.986us 1 1 100.00
otbn_csr_aliasing 5.000s 43.023us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 129.000s 53609.775us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 29.000s 599.472us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 22.000s 64.813us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 53.000s 187.972us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 20.000s 56.219us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 8.000s 69.713us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 9.000s 68.792us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 5.000s 17.954us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 10.000s 32.846us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 8.000s 21.338us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 4.000s 16.872us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 6.000s 130.566us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 6.000s 130.566us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 6.000s 22.032us 1 1 100.00
otbn_csr_rw 4.000s 49.986us 1 1 100.00
otbn_csr_aliasing 5.000s 43.023us 1 1 100.00
otbn_same_csr_outstanding 4.000s 18.859us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 6.000s 22.032us 1 1 100.00
otbn_csr_rw 4.000s 49.986us 1 1 100.00
otbn_csr_aliasing 5.000s 43.023us 1 1 100.00
otbn_same_csr_outstanding 4.000s 18.859us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 7.000s 149.800us 1 1 100.00
otbn_dmem_err 11.000s 27.109us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 16.000s 212.892us 1 1 100.00
otbn_controller_ispr_rdata_err 12.000s 61.470us 1 1 100.00
otbn_mac_bignum_acc_err 9.000s 105.046us 1 1 100.00
otbn_urnd_err 5.000s 37.553us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 6.000s 109.583us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 6.000s 141.854us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 7.000s 25.682us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 362.000s 6952.253us 1 1 100.00
otbn_tl_intg_err 16.000s 128.177us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 24.000s 195.601us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 362.000s 6952.253us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 362.000s 6952.253us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 10.000s 144.298us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 11.000s 27.109us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 7.000s 149.800us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 16.000s 128.177us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 9.000s 68.792us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 7.000s 149.800us 1 1 100.00
otbn_dmem_err 11.000s 27.109us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 17.954us 1 1 100.00
otbn_illegal_mem_acc 6.000s 109.583us 1 1 100.00
otbn_sec_cm 362.000s 6952.253us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 362.000s 6952.253us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 8.000s 36.496us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 7.000s 149.800us 1 1 100.00
otbn_dmem_err 11.000s 27.109us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 17.954us 1 1 100.00
otbn_illegal_mem_acc 6.000s 109.583us 1 1 100.00
otbn_sec_cm 362.000s 6952.253us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 362.000s 6952.253us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 9.000s 68.792us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 7.000s 149.800us 1 1 100.00
otbn_dmem_err 11.000s 27.109us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 17.954us 1 1 100.00
otbn_illegal_mem_acc 6.000s 109.583us 1 1 100.00
otbn_sec_cm 362.000s 6952.253us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 362.000s 6952.253us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 8.000s 36.496us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 9.000s 555.677us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 8.000s 39.249us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 28.000s 206.685us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 28.000s 206.685us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 9.000s 17.197us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 362.000s 6952.253us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 362.000s 6952.253us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 9.000s 863.409us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 362.000s 6952.253us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 362.000s 6952.253us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 21.000s 179.013us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 21.000s 179.013us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 5.000s 27.428us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 8.000s 36.496us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 8.000s 36.496us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 8.000s 36.496us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 20.000s 56.219us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 8.000s 36.496us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 8.000s 36.496us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 27.000s 74.597us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 8.000s 36.496us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 362.000s 6952.253us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 197.000s 4278.618us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 32.247us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) 1 test run
otbn_stress_all_with_rand_reset 52055091704107438033546000322510366977683294291709598913707443222228224486313 284
UVM_INFO @ 4278618048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---