Simulation Results: otp_ctrl

 
15/07/2026 19:40:28 DVSim: v1.49.12 sha: 62fb2eb json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 73.64 %
  • code
  • 72.40 %
  • assert
  • 94.13 %
  • func
  • 54.39 %
  • line
  • 87.48 %
  • branch
  • 84.14 %
  • cond
  • 86.17 %
  • toggle
  • 65.97 %
  • FSM
  • 38.23 %
Validation stages
V1
77.78%
V2
75.00%
V2S
77.78%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.700s 104.438us 1 1 100.00
smoke 0 1 0.00
otp_ctrl_smoke 3.150s 80.341us 0 1 0.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.590s 214.083us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.840s 54.608us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 3.490s 112.388us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 8.100s 3458.084us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.010s 500.696us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.840s 54.608us 1 1 100.00
otp_ctrl_csr_aliasing 8.100s 3458.084us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 2.060s 43.226us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.420s 79.311us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 118.900s 46429.693us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 4.470s 2757.626us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 6.530s 765.561us 1 1 100.00
otp_ctrl_check_fail 1.680s 150.710us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 5.020s 388.041us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 14.530s 990.630us 1 1 100.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 6.980s 528.621us 0 1 0.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 11.530s 556.941us 1 1 100.00
otp_ctrl_parallel_lc_esc 19.940s 537.051us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 57.880s 32852.723us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 4.870s 637.966us 1 1 100.00
test_access 0 1 0.00
otp_ctrl_test_access 12.910s 6383.814us 0 1 0.00
stress_all 0 1 0.00
otp_ctrl_stress_all 38.650s 5752.455us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.620s 101.679us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.020s 76.080us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 5.760s 404.710us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 5.760s 404.710us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.590s 214.083us 1 1 100.00
otp_ctrl_csr_rw 1.840s 54.608us 1 1 100.00
otp_ctrl_csr_aliasing 8.100s 3458.084us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.660s 598.962us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.590s 214.083us 1 1 100.00
otp_ctrl_csr_rw 1.840s 54.608us 1 1 100.00
otp_ctrl_csr_aliasing 8.100s 3458.084us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.660s 598.962us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 278.000s 30826.843us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 278.000s 30826.843us 1 1 100.00
otp_ctrl_tl_intg_err 21.640s 1488.695us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 278.000s 30826.843us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 278.000s 30826.843us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 21.640s 1488.695us 1 1 100.00
sec_cm_secret_mem_scramble 0 1 0.00
otp_ctrl_smoke 3.150s 80.341us 0 1 0.00
sec_cm_part_mem_digest 0 1 0.00
otp_ctrl_smoke 3.150s 80.341us 0 1 0.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 278.000s 30826.843us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 278.000s 30826.843us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 278.000s 30826.843us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 278.000s 30826.843us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 278.000s 30826.843us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 278.000s 30826.843us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 278.000s 30826.843us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 278.000s 30826.843us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 278.000s 30826.843us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 278.000s 30826.843us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 278.000s 30826.843us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 278.000s 30826.843us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 278.000s 30826.843us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 278.000s 30826.843us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 278.000s 30826.843us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 19.940s 537.051us 1 1 100.00
otp_ctrl_sec_cm 278.000s 30826.843us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 19.940s 537.051us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 19.940s 537.051us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 19.940s 537.051us 1 1 100.00
otp_ctrl_macro_errs 4.870s 637.966us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 19.940s 537.051us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 19.940s 537.051us 1 1 100.00
otp_ctrl_sec_cm 278.000s 30826.843us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 19.940s 537.051us 1 1 100.00
otp_ctrl_sec_cm 278.000s 30826.843us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 19.940s 537.051us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 19.940s 537.051us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 19.940s 537.051us 1 1 100.00
otp_ctrl_macro_errs 4.870s 637.966us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 19.940s 537.051us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 19.940s 537.051us 1 1 100.00
otp_ctrl_sec_cm 278.000s 30826.843us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 4.470s 2757.626us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 1.680s 150.710us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 14.530s 990.630us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 14.530s 990.630us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 14.530s 990.630us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 14.530s 990.630us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 14.530s 990.630us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
otp_ctrl_smoke 3.150s 80.341us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 14.530s 990.630us 1 1 100.00
sec_cm_test_bus_lc_gated 0 1 0.00
otp_ctrl_smoke 3.150s 80.341us 0 1 0.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 278.000s 30826.843us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 5.020s 388.041us 1 1 100.00
sec_cm_check_trigger_config_regwen 0 1 0.00
otp_ctrl_smoke 3.150s 80.341us 0 1 0.00
sec_cm_check_config_regwen 0 1 0.00
otp_ctrl_smoke 3.150s 80.341us 0 1 0.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 4.870s 637.966us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 105.410s 68914.473us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 3.070s 707.325us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 2 test runs
otp_ctrl_smoke 103633793618351581540357159783630890480319663831175489075251856143226368043369 3096
UVM_INFO @ 80341213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_partition_walk 46797150543608172464229573120086674158245426016892732638127383155968827710554 160055
UVM_INFO @ 46429693447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 2 test runs
otp_ctrl_check_fail 26612343233066506956398496782937723637228248853221712930427955708073432549769 210
UVM_INFO @ 150709821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 22778876126247766404395550159030034506417596655943892933573298759039657337535 11841
UVM_INFO @ 6383814243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 23241401033615965909364779510383470980662665549090496573729903584676617640885 89
UVM_INFO @ 68914472594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 1 test run
otp_ctrl_parallel_key_req 50437874042046255879604247906013903810213303976271587697095096219695825295925 6767
UVM_INFO @ 528620625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:2213) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_stress_all_with_rand_reset 63309426643184068621654835895940098289293593859264300913440716736950799997530 157
UVM_INFO @ 707324515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:671) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr 1 test run
otp_ctrl_stress_all 29851827669721443583762224606485185374837355583997709990100418007703051620084 38488
UVM_INFO @ 5752454838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_csr_mem_rw_with_rand_reset 55230979606795141625640494591141373792646105850393678683973426693135274899049 91
UVM_INFO @ 500695697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---