Simulation Results: rom_ctrl/32kb

 
15/07/2026 19:40:28 DVSim: v1.49.12 sha: 62fb2eb json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.72 %
  • code
  • 89.88 %
  • assert
  • 97.09 %
  • func
  • 97.18 %
  • block
  • 92.51 %
  • line
  • 91.73 %
  • branch
  • 92.74 %
  • toggle
  • 84.57 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
88.89%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 3.000s 285.228us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 3.000s 386.267us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 9.000s 299.450us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.000s 360.758us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 1816.434us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.000s 320.887us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 9.000s 299.450us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 1816.434us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 8.000s 555.357us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.000s 219.634us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 3.000s 167.024us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 7.000s 332.326us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 5.000s 218.285us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 4.000s 128.957us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 6.000s 675.114us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 6.000s 675.114us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.000s 386.267us 1 1 100.00
rom_ctrl_csr_rw 9.000s 299.450us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 1816.434us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.000s 171.724us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.000s 386.267us 1 1 100.00
rom_ctrl_csr_rw 9.000s 299.450us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 1816.434us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.000s 171.724us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 5.000s 186.499us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 11.000s 584.015us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 98.000s 1794.574us 1 1 100.00
rom_ctrl_tl_intg_err 26.000s 2172.037us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 98.000s 1794.574us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 98.000s 1794.574us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 5.000s 186.499us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 5.000s 186.499us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 5.000s 186.499us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 5.000s 186.499us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 5.000s 186.499us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 98.000s 1794.574us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 98.000s 1794.574us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 3.000s 285.228us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 3.000s 285.228us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 3.000s 285.228us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 26.000s 2172.037us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 5.000s 186.499us 0 1 0.00
rom_ctrl_kmac_err_chk 5.000s 218.285us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 5.000s 186.499us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 5.000s 186.499us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 5.000s 186.499us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 11.000s 584.015us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 98.000s 1794.574us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 43.000s 2704.740us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 52113946315347606671004419236012759922203410271901041372698940784246938187403 88
UVM_INFO @ 167023838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) 1 test run
rom_ctrl_corrupt_sig_fatal_chk 29188020327288063400011472865592911008332647488156687823997788702743751599173 87
UVM_INFO @ 186499159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---