Simulation Results: rom_ctrl/64kb

 
15/07/2026 19:40:28 DVSim: v1.49.12 sha: 62fb2eb json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.87 %
  • code
  • 90.99 %
  • assert
  • 97.38 %
  • func
  • 96.24 %
  • block
  • 95.55 %
  • line
  • 95.81 %
  • branch
  • 93.01 %
  • toggle
  • 84.65 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 8.000s 1087.046us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 12.000s 5503.763us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 5.000s 214.175us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 5.000s 1873.106us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 5.000s 370.639us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.000s 304.143us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 5.000s 214.175us 1 1 100.00
rom_ctrl_csr_aliasing 5.000s 370.639us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 4.000s 297.487us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 10.000s 294.989us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 6.000s 988.127us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 16.000s 765.610us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 8.000s 1370.457us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 4.000s 700.036us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 18.000s 556.697us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 18.000s 556.697us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 12.000s 5503.763us 1 1 100.00
rom_ctrl_csr_rw 5.000s 214.175us 1 1 100.00
rom_ctrl_csr_aliasing 5.000s 370.639us 1 1 100.00
rom_ctrl_same_csr_outstanding 16.000s 2365.946us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 12.000s 5503.763us 1 1 100.00
rom_ctrl_csr_rw 5.000s 214.175us 1 1 100.00
rom_ctrl_csr_aliasing 5.000s 370.639us 1 1 100.00
rom_ctrl_same_csr_outstanding 16.000s 2365.946us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 74.000s 6428.122us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 15.000s 776.178us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 198.000s 2852.318us 1 1 100.00
rom_ctrl_tl_intg_err 31.000s 391.192us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 198.000s 2852.318us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 198.000s 2852.318us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 74.000s 6428.122us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 74.000s 6428.122us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 74.000s 6428.122us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 74.000s 6428.122us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 74.000s 6428.122us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 198.000s 2852.318us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 198.000s 2852.318us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 8.000s 1087.046us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 8.000s 1087.046us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 8.000s 1087.046us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 31.000s 391.192us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 74.000s 6428.122us 1 1 100.00
rom_ctrl_kmac_err_chk 8.000s 1370.457us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 74.000s 6428.122us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 74.000s 6428.122us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 74.000s 6428.122us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 15.000s 776.178us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 198.000s 2852.318us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 56.000s 12109.771us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 10145028718509682501493982165363883586288048327271252964374309790718347667725 88
UVM_INFO @ 988126865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---