Simulation Results: rstmgr

 
15/07/2026 19:40:28 DVSim: v1.49.12 sha: 62fb2eb json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.90 %
  • code
  • 99.13 %
  • assert
  • 98.17 %
  • func
  • 96.39 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.30 %
  • toggle
  • 99.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.410s 65.200us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.970s 64.666us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.930s 37.307us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 4.840s 236.587us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.410s 51.927us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.240s 101.630us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.930s 37.307us 1 1 100.00
rstmgr_csr_aliasing 1.410s 51.927us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.410s 156.931us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.040s 38.127us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.000s 83.780us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.430s 559.667us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.430s 559.667us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.430s 559.667us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.430s 559.667us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 19.590s 3165.274us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.840s 36.820us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.890s 63.686us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.890s 63.686us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.970s 64.666us 1 1 100.00
rstmgr_csr_rw 0.930s 37.307us 1 1 100.00
rstmgr_csr_aliasing 1.410s 51.927us 1 1 100.00
rstmgr_same_csr_outstanding 1.290s 66.517us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.970s 64.666us 1 1 100.00
rstmgr_csr_rw 0.930s 37.307us 1 1 100.00
rstmgr_csr_aliasing 1.410s 51.927us 1 1 100.00
rstmgr_same_csr_outstanding 1.290s 66.517us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 28.890s 6832.951us 1 1 100.00
rstmgr_tl_intg_err 3.870s 325.771us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 28.890s 6832.951us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 28.890s 6832.951us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 3.870s 325.771us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.070s 66.999us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 3.870s 482.003us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.990s 292.130us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 28.890s 6832.951us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.930s 37.307us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.930s 37.307us 1 1 100.00