Simulation Results: rv_dm/use_dmi_interface

 
15/07/2026 19:40:28 DVSim: v1.49.12 sha: 62fb2eb json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.33 %
  • code
  • 73.37 %
  • assert
  • 96.59 %
  • func
  • 92.02 %
  • block
  • 89.58 %
  • line
  • 89.27 %
  • branch
  • 71.71 %
  • toggle
  • 71.80 %
  • FSM
  • 60.71 %
Validation stages
V1
96.30%
V2
69.57%
V2S
85.71%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rv_dm_smoke 34.000s 2959.534us 1 1 100.00
jtag_dtm_csr_hw_reset 1 1 100.00
rv_dm_jtag_dtm_csr_hw_reset 32.000s 243.510us 1 1 100.00
jtag_dtm_csr_rw 1 1 100.00
rv_dm_jtag_dtm_csr_rw 36.000s 714.639us 1 1 100.00
jtag_dtm_csr_bit_bash 1 1 100.00
rv_dm_jtag_dtm_csr_bit_bash 42.000s 8057.352us 1 1 100.00
jtag_dtm_csr_aliasing 1 1 100.00
rv_dm_jtag_dtm_csr_aliasing 37.000s 2107.058us 1 1 100.00
jtag_dmi_csr_hw_reset 1 1 100.00
rv_dm_jtag_dmi_csr_hw_reset 37.000s 21316.858us 1 1 100.00
jtag_dmi_csr_rw 1 1 100.00
rv_dm_jtag_dmi_csr_rw 32.000s 2040.980us 1 1 100.00
jtag_dmi_csr_bit_bash 1 1 100.00
rv_dm_jtag_dmi_csr_bit_bash 37.000s 7985.174us 1 1 100.00
jtag_dmi_csr_aliasing 1 1 100.00
rv_dm_jtag_dmi_csr_aliasing 56.000s 169624.304us 1 1 100.00
jtag_dmi_cmderr_busy 1 1 100.00
rv_dm_cmderr_busy 32.000s 535.477us 1 1 100.00
jtag_dmi_cmderr_not_supported 1 1 100.00
rv_dm_cmderr_not_supported 33.000s 136.032us 1 1 100.00
cmderr_exception 1 1 100.00
rv_dm_cmderr_exception 32.000s 488.673us 1 1 100.00
mem_tl_access_resuming 0 1 0.00
rv_dm_mem_tl_access_resuming 33.000s 108.870us 0 1 0.00
mem_tl_access_halted 1 1 100.00
rv_dm_mem_tl_access_halted 35.000s 152.094us 1 1 100.00
cmderr_halt_resume 1 1 100.00
rv_dm_cmderr_halt_resume 31.000s 658.165us 1 1 100.00
dataaddr_rw_access 1 1 100.00
rv_dm_dataaddr_rw_access 32.000s 79.297us 1 1 100.00
halt_resume 1 1 100.00
rv_dm_halt_resume_whereto 35.000s 639.997us 1 1 100.00
progbuf_busy 1 1 100.00
rv_dm_cmderr_busy 32.000s 535.477us 1 1 100.00
abstractcmd_status 1 1 100.00
rv_dm_abstractcmd_status 30.000s 190.331us 1 1 100.00
progbuf_read_write_execute 1 1 100.00
rv_dm_progbuf_read_write_execute 32.000s 396.491us 1 1 100.00
progbuf_exception 1 1 100.00
rv_dm_cmderr_exception 32.000s 488.673us 1 1 100.00
rom_read_access 1 1 100.00
rv_dm_rom_read_access 31.000s 69.830us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_dm_csr_hw_reset 31.000s 1069.689us 1 1 100.00
csr_rw 1 1 100.00
rv_dm_csr_rw 33.000s 524.203us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_dm_csr_bit_bash 51.000s 10517.393us 1 1 100.00
csr_aliasing 1 1 100.00
rv_dm_csr_aliasing 55.000s 4618.730us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_dm_csr_mem_rw_with_rand_reset 35.000s 193.682us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_dm_csr_aliasing 55.000s 4618.730us 1 1 100.00
rv_dm_csr_rw 33.000s 524.203us 1 1 100.00
mem_walk 1 1 100.00
rv_dm_mem_walk 43.000s 38.334us 1 1 100.00
mem_partial_access 1 1 100.00
rv_dm_mem_partial_access 30.000s 120.971us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
idcode 1 1 100.00
rv_dm_smoke 34.000s 2959.534us 1 1 100.00
jtag_dtm_hard_reset 1 1 100.00
rv_dm_jtag_dtm_hard_reset 35.000s 148.524us 1 1 100.00
jtag_dtm_idle_hint 1 1 100.00
rv_dm_jtag_dtm_idle_hint 33.000s 343.594us 1 1 100.00
jtag_dmi_failed_op 1 1 100.00
rv_dm_dmi_failed_op 31.000s 150.044us 1 1 100.00
jtag_dmi_dm_inactive 1 1 100.00
rv_dm_jtag_dmi_dm_inactive 33.000s 1696.829us 1 1 100.00
sba 0 2 0.00
rv_dm_sba_tl_access 45.000s 15922.009us 0 1 0.00
rv_dm_delayed_resp_sba_tl_access 31.000s 490.914us 0 1 0.00
bad_sba 0 1 0.00
rv_dm_bad_sba_tl_access 48.000s 9616.140us 0 1 0.00
sba_autoincrement 0 1 0.00
rv_dm_autoincr_sba_tl_access 122.000s 153024.267us 0 1 0.00
jtag_dmi_debug_disabled 0 1 0.00
rv_dm_jtag_dmi_debug_disabled 30.000s 118.283us 0 1 0.00
sba_debug_disabled 1 1 100.00
rv_dm_sba_debug_disabled 36.000s 1092.089us 1 1 100.00
ndmreset_req 1 1 100.00
rv_dm_ndmreset_req 31.000s 183.585us 1 1 100.00
hart_unavail 0 1 0.00
rv_dm_hart_unavail 30.000s 170.845us 0 1 0.00
tap_ctrl_transitions 2 2 100.00
rv_dm_tap_fsm 37.000s 8274.416us 1 1 100.00
rv_dm_tap_fsm_rand_reset 50.000s 7166.869us 1 1 100.00
hartsel_warl 1 1 100.00
rv_dm_hartsel_warl 31.000s 101.227us 1 1 100.00
stress_all 0 1 0.00
rv_dm_stress_all 29.000s 89.976us 0 1 0.00
alert_test 1 1 100.00
rv_dm_alert_test 31.000s 31.653us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_dm_tl_errors 32.000s 160.965us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_dm_tl_errors 32.000s 160.965us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_dm_csr_aliasing 55.000s 4618.730us 1 1 100.00
rv_dm_csr_hw_reset 31.000s 1069.689us 1 1 100.00
rv_dm_csr_rw 33.000s 524.203us 1 1 100.00
rv_dm_same_csr_outstanding 35.000s 562.200us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_dm_csr_aliasing 55.000s 4618.730us 1 1 100.00
rv_dm_csr_hw_reset 31.000s 1069.689us 1 1 100.00
rv_dm_csr_rw 33.000s 524.203us 1 1 100.00
rv_dm_same_csr_outstanding 35.000s 562.200us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_dm_sec_cm 31.000s 362.994us 1 1 100.00
rv_dm_tl_intg_err 33.000s 716.462us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_dm_tl_intg_err 33.000s 716.462us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 2 50.00
rv_dm_sba_debug_disabled 36.000s 1092.089us 1 1 100.00
rv_dm_debug_disabled 30.000s 51.255us 0 1 0.00
sec_cm_lc_dft_en_intersig_mubi 1 2 50.00
rv_dm_sba_debug_disabled 36.000s 1092.089us 1 1 100.00
rv_dm_debug_disabled 30.000s 51.255us 0 1 0.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 1 1 100.00
rv_dm_smoke 34.000s 2959.534us 1 1 100.00
sec_cm_dm_en_ctrl_lc_gated 1 1 100.00
rv_dm_buffered_enable 31.000s 243.822us 1 1 100.00
sec_cm_sba_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 30.000s 252.516us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 30.000s 252.516us 1 1 100.00
sec_cm_exec_ctrl_mubi 1 1 100.00
rv_dm_buffered_enable 31.000s 243.822us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rv_dm_stress_all_with_rand_reset 46.000s 1018.325us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
rv_dm_scanmode 177.000s 300000.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared: 3 test runs
rv_dm_sba_tl_access 26123411771213605352218301738214585782715608920114760132800867551711131514629 87
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @23821
rv_dm_bad_sba_tl_access 71231816216357340014625068410210724282366834409274752703130743891967816652297 96
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @23835
rv_dm_autoincr_sba_tl_access 35299327120301244621308521754730022649704923445603158549695132222285070611509 87
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @23940
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) 2 test runs
rv_dm_jtag_dmi_debug_disabled 91219123433939612130711685244995915591643828620385365133420822492078765705286 87
UVM_INFO @ 118283000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 29759135920574065258661164898220634508843464808835237950916634977403045886297 88
UVM_INFO @ 89975592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp 1 test run
rv_dm_delayed_resp_sba_tl_access 104371548248991852113305368043613775930521683180346288322320507576641845709675 107
UVM_INFO @ 490914355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == *'b* (* [*] vs * [*]) 1 test run
rv_dm_mem_tl_access_resuming 1182847206717335338157112478808942063919188818481965619224557076520981722325 87
UVM_INFO @ 108870291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [*] vs * [*]) 1 test run
rv_dm_hart_unavail 34300469593734910663943821495816559238630004822183870331942294550520804873007 87
UVM_INFO @ 170844724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_rv_dm_sva_*/rv_dm_enable_checker.sv,42): Assertion DebugRequestNeedsDebug_A has failed 1 test run
rv_dm_debug_disabled 54663414395735425975703708977487868443491003163544586946785583616109534538877 90
UVM_ERROR @ 51255476 ps: (rv_dm_debug_disabled_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_debug_disabled_vseq] Check failed (rvalue == expected_output)
UVM_INFO @ 51255476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
rv_dm_scanmode 35796131619626022317177208513513087333302898405805616414736926146018376776514 87
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_dm_common_vseq] Check failed (vseq_done) 1 test run
rv_dm_stress_all_with_rand_reset 67000601420852859992654764114044022678677993587113728694738398849918090739825 103
UVM_INFO @ 1018324833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---