Simulation Results: rv_timer

 
15/07/2026 19:40:28 DVSim: v1.49.12 sha: 62fb2eb json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 98.09 %
  • code
  • 95.85 %
  • assert
  • 98.42 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 89.26 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.000s 47.185us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 77.195us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 2.000s 11.474us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.000s 614.194us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.000s 18.545us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 2.000s 121.099us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 2.000s 11.474us 1 1 100.00
rv_timer_csr_aliasing 1.000s 18.545us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 2.000s 352.561us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 3.000s 3219.497us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 52.000s 188253.791us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 52.000s 188253.791us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 7.000s 953.479us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 1.000s 43.935us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 1.000s 29.132us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.000s 297.065us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.000s 297.065us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 77.195us 1 1 100.00
rv_timer_csr_rw 2.000s 11.474us 1 1 100.00
rv_timer_csr_aliasing 1.000s 18.545us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 18.359us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 77.195us 1 1 100.00
rv_timer_csr_rw 2.000s 11.474us 1 1 100.00
rv_timer_csr_aliasing 1.000s 18.545us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 18.359us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 1.000s 150.800us 1 1 100.00
rv_timer_tl_intg_err 1.000s 450.633us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.000s 450.633us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 1.000s 359.112us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 1.000s 164.911us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 36.000s 6975.831us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 37987286491535507396995397633309239814165392983048295353379620134577795226437 86
UVM_INFO @ 359111894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 60958621961234796016659593144627544357105613777178616064127646762223217278806 84
UVM_INFO @ 352561276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:347) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) 1 test run
rv_timer_max 56519609753205349212227464682859866242760979728114367487715107752312501426117 84
UVM_INFO @ 164910564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---