Simulation Results: sram_ctrl/ret

 
15/07/2026 19:40:28 DVSim: v1.49.12 sha: 62fb2eb json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.30 %
  • code
  • 81.58 %
  • assert
  • 97.12 %
  • func
  • 95.20 %
  • block
  • 92.75 %
  • line
  • 93.79 %
  • branch
  • 87.64 %
  • toggle
  • 78.23 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 76.549us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 114.637us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 45.347us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 201.393us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 30.882us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 39.730us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 45.347us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 30.882us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 10.000s 3539.239us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 5.000s 192.187us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 2.000s 62.920us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 104.000s 8298.991us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 6.000s 1133.685us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 20.000s 843.540us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 3.000s 307.474us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 5.000s 451.017us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 128.381us 1 1 100.00
sram_ctrl_partial_access_b2b 178.000s 14213.365us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 1.000s 34.216us 0 1 0.00
sram_ctrl_throughput_w_partial_write 2.000s 52.243us 0 1 0.00
sram_ctrl_throughput_w_readback 8.000s 30.311us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 8.000s 2558.778us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 65.518us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 21.000s 4087.678us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 15.970us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 42.321us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 42.321us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 114.637us 1 1 100.00
sram_ctrl_csr_rw 1.000s 45.347us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 30.882us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 17.863us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 114.637us 1 1 100.00
sram_ctrl_csr_rw 1.000s 45.347us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 30.882us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 17.863us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 855.243us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 1200.788us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 821.714us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 1200.788us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 821.714us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 2558.778us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 2558.778us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 45.347us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 5.000s 451.017us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 5.000s 451.017us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 5.000s 451.017us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 3.000s 307.474us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.000s 81.103us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 855.243us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.000s 44.017us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 76.549us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 76.549us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 5.000s 451.017us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 1200.788us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 3.000s 307.474us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 1200.788us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 1200.788us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 76.549us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 1200.788us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 21.000s 459.669us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 105959817377827897645997026628589860627627768447054962903153175881794371392085 86
UVM_INFO @ 34215944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 26974513840513446077212181209357242734019379974674729277027623861068222201500 86
UVM_INFO @ 52242977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 63206975648729891848259590648081644586621891751246728072080448524712911641332 86
UVM_INFO @ 30311008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---