Simulation Results

Simulation Results: uart

15/07/2026 19:40:28 DVSim: v1.49.12 sha: 62fb2eb json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
93.93 %

code
92.53 %

assert
98.56 %

func
90.69 %

block
98.83 %

line
99.24 %

branch
97.79 %

toggle
73.08 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		95.45%
V2S		100.00%
V3		0.00%

6/6 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	uart_smoke	8.000s	6286.076us	1	1	100.00
csr_hw_reset				1	1	100.00
	uart_csr_hw_reset	1.000s	54.735us	1	1	100.00
csr_rw				1	1	100.00
	uart_csr_rw	1.000s	50.570us	1	1	100.00
csr_bit_bash				1	1	100.00
	uart_csr_bit_bash	3.000s	325.127us	1	1	100.00
csr_aliasing				1	1	100.00
	uart_csr_aliasing	1.000s	24.518us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	uart_csr_mem_rw_with_rand_reset	7.000s	55.817us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	uart_csr_rw	1.000s	50.570us	1	1	100.00
	uart_csr_aliasing	1.000s	24.518us	1	1	100.00

21/22 passed

95.45 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
base_random_seq				1	1	100.00
	uart_tx_rx	30.000s	194675.430us	1	1	100.00
parity				2	2	100.00
	uart_smoke	8.000s	6286.076us	1	1	100.00
	uart_tx_rx	30.000s	194675.430us	1	1	100.00
parity_error				2	2	100.00
	uart_intr	31.000s	47455.382us	1	1	100.00
	uart_rx_parity_err	158.000s	131341.342us	1	1	100.00
watermark				2	2	100.00
	uart_tx_rx	30.000s	194675.430us	1	1	100.00
	uart_intr	31.000s	47455.382us	1	1	100.00
fifo_full				1	1	100.00
	uart_fifo_full	18.000s	26562.330us	1	1	100.00
fifo_overflow				1	1	100.00
	uart_fifo_overflow	24.000s	83580.238us	1	1	100.00
fifo_reset				1	1	100.00
	uart_fifo_reset	74.000s	186471.622us	1	1	100.00
rx_frame_err				1	1	100.00
	uart_intr	31.000s	47455.382us	1	1	100.00
rx_break_err				1	1	100.00
	uart_intr	31.000s	47455.382us	1	1	100.00
rx_timeout				1	1	100.00
	uart_intr	31.000s	47455.382us	1	1	100.00
perf				1	1	100.00
	uart_perf	75.000s	22580.331us	1	1	100.00
sys_loopback				1	1	100.00
	uart_loopback	8.000s	8832.493us	1	1	100.00
line_loopback				1	1	100.00
	uart_loopback	8.000s	8832.493us	1	1	100.00
rx_noise_filter				0	1	0.00
	uart_noise_filter	23.000s	68424.370us	0	1	0.00
rx_start_bit_filter				1	1	100.00
	uart_rx_start_bit_filter	2.000s	1588.111us	1	1	100.00
tx_overide				1	1	100.00
	uart_tx_ovrd	2.000s	465.254us	1	1	100.00
rx_oversample				1	1	100.00
	uart_rx_oversample	9.000s	6183.912us	1	1	100.00
long_b2b_transfer				1	1	100.00
	uart_long_xfer_wo_dly	145.000s	39525.483us	1	1	100.00
stress_all				1	1	100.00
	uart_stress_all	94.000s	65388.221us	1	1	100.00
alert_test				1	1	100.00
	uart_alert_test	2.000s	36.426us	1	1	100.00
intr_test				1	1	100.00
	uart_intr_test	1.000s	14.063us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	uart_tl_errors	2.000s	245.569us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	uart_tl_errors	2.000s	245.569us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	uart_csr_hw_reset	1.000s	54.735us	1	1	100.00
	uart_csr_rw	1.000s	50.570us	1	1	100.00
	uart_csr_aliasing	1.000s	24.518us	1	1	100.00
	uart_same_csr_outstanding	1.000s	14.002us	1	1	100.00
tl_d_partial_access				4	4	100.00
	uart_csr_hw_reset	1.000s	54.735us	1	1	100.00
	uart_csr_rw	1.000s	50.570us	1	1	100.00
	uart_csr_aliasing	1.000s	24.518us	1	1	100.00
	uart_same_csr_outstanding	1.000s	14.002us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	uart_sec_cm	1.000s	146.424us	1	1	100.00
	uart_tl_intg_err	1.000s	105.856us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	uart_tl_intg_err	1.000s	105.856us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	uart_stress_all_with_rand_reset	15.000s	2499.134us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uart_scoreboard.sv:395) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [] vs []) check rx_idle fail: rx_en = , uart_rx_clk_pulses = *				2 test runs
	uart_noise_filter	80015933356322861522531509554880811490066295030222987215118242239298699869363	85	UVM_ERROR @ 4722449656 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 4722449656 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_INFO @ 27072329656 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 3/10 UVM_INFO @ 28606409656 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 4/10
	uart_stress_all_with_rand_reset	102574729032042410944474663335031147382680786498603505955522549726706590837007	116	UVM_ERROR @ 2412653995 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0 UVM_ERROR @ 2412693995 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 2412813995 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata UVM_ERROR @ 2422513995 ps: (uart_scoreboard.sv:446) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr