Simulation Results: ac_range_check

 
16/07/2026 19:40:29 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.85 %
  • code
  • 93.00 %
  • assert
  • 97.75 %
  • func
  • 57.79 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 80.82 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 20.000s 2039.067us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 47.000s 10811.523us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 48.256us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 3.000s 40.883us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 21.000s 709.811us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 19.000s 1342.213us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 2.000s 125.246us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 3.000s 40.883us 1 1 100.00
ac_range_check_csr_aliasing 19.000s 1342.213us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 2.000s 675.667us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 19.000s 505.331us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 161.000s 35271.167us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 1.000s 15.307us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 2.000s 94.522us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 2.000s 328.319us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 2.000s 328.319us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 48.256us 1 1 100.00
ac_range_check_csr_rw 3.000s 40.883us 1 1 100.00
ac_range_check_csr_aliasing 19.000s 1342.213us 1 1 100.00
ac_range_check_same_csr_outstanding 3.000s 57.055us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 48.256us 1 1 100.00
ac_range_check_csr_rw 3.000s 40.883us 1 1 100.00
ac_range_check_csr_aliasing 19.000s 1342.213us 1 1 100.00
ac_range_check_same_csr_outstanding 3.000s 57.055us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 11.000s 1775.355us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 11.000s 1775.355us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 11.000s 1775.355us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 11.000s 1775.355us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 84.000s 17293.895us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 2.000s 13.721us 1 1 100.00
ac_range_check_tl_intg_err 7.000s 381.019us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 251.000s 9679.307us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 19.000s 973.572us 1 1 100.00