Simulation Results: aes/gcm_masked

 
16/07/2026 19:40:29 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.02 %
  • code
  • 95.08 %
  • assert
  • 98.29 %
  • func
  • 64.68 %
  • block
  • 95.70 %
  • line
  • 97.37 %
  • branch
  • 89.40 %
  • toggle
  • 98.05 %
  • FSM
  • 95.48 %
Validation stages
V1
100.00%
V2
94.74%
V2S
83.33%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 3.000s 158.589us 1 1 100.00
smoke 1 1 100.00
aes_smoke 4.000s 94.027us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 6.000s 61.513us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 94.053us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 6.000s 1305.325us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 97.614us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 52.155us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 94.053us 1 1 100.00
aes_csr_aliasing 3.000s 97.614us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 4.000s 94.027us 1 1 100.00
aes_config_error 5.000s 852.938us 1 1 100.00
aes_stress 4.000s 118.736us 1 1 100.00
key_length 3 3 100.00
aes_smoke 4.000s 94.027us 1 1 100.00
aes_config_error 5.000s 852.938us 1 1 100.00
aes_stress 4.000s 118.736us 1 1 100.00
back2back 2 2 100.00
aes_stress 4.000s 118.736us 1 1 100.00
aes_b2b 4.000s 169.319us 1 1 100.00
backpressure 1 1 100.00
aes_stress 4.000s 118.736us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 4.000s 94.027us 1 1 100.00
aes_config_error 5.000s 852.938us 1 1 100.00
aes_stress 4.000s 118.736us 1 1 100.00
aes_alert_reset 3.000s 125.976us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 60.537us 1 1 100.00
aes_config_error 5.000s 852.938us 1 1 100.00
aes_alert_reset 3.000s 125.976us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 4.000s 72.981us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 7.000s 1230.771us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 7.000s 210.993us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 125.976us 1 1 100.00
stress 1 1 100.00
aes_stress 4.000s 118.736us 1 1 100.00
sideload 2 2 100.00
aes_stress 4.000s 118.736us 1 1 100.00
aes_sideload 3.000s 304.301us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 4.000s 134.067us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 2.000s 47.279us 0 1 0.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 3.000s 245.472us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 110.514us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 65.522us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 65.522us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 6.000s 61.513us 1 1 100.00
aes_csr_rw 2.000s 94.053us 1 1 100.00
aes_csr_aliasing 3.000s 97.614us 1 1 100.00
aes_same_csr_outstanding 3.000s 423.354us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 6.000s 61.513us 1 1 100.00
aes_csr_rw 2.000s 94.053us 1 1 100.00
aes_csr_aliasing 3.000s 97.614us 1 1 100.00
aes_same_csr_outstanding 3.000s 423.354us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 68.000s 4753.646us 0 1 0.00
fault_inject 1 3 33.33
aes_fi 4.000s 163.357us 0 1 0.00
aes_control_fi 2.000s 47.201us 1 1 100.00
aes_cipher_fi 18.000s 10017.271us 0 1 0.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 3.000s 137.406us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 3.000s 137.406us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 3.000s 137.406us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 3.000s 137.406us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 406.461us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 1002.099us 1 1 100.00
aes_tl_intg_err 3.000s 203.993us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 203.993us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 125.976us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 137.406us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 137.406us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 4.000s 94.027us 1 1 100.00
aes_stress 4.000s 118.736us 1 1 100.00
aes_alert_reset 3.000s 125.976us 1 1 100.00
aes_core_fi 3.000s 521.988us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 3.000s 245.472us 1 1 100.00
aes_config_error 5.000s 852.938us 1 1 100.00
aes_stress 4.000s 118.736us 1 1 100.00
aes_core_fi 3.000s 521.988us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 137.406us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 87.927us 1 1 100.00
aes_stress 4.000s 118.736us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 4.000s 118.736us 1 1 100.00
aes_sideload 3.000s 304.301us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 87.927us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 87.927us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 87.927us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 87.927us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 87.927us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 4.000s 118.736us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 4.000s 118.736us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 4.000s 163.357us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 4.000s 163.357us 0 1 0.00
aes_control_fi 2.000s 47.201us 1 1 100.00
aes_cipher_fi 18.000s 10017.271us 0 1 0.00
aes_ctr_fi 2.000s 72.820us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 4.000s 163.357us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 4.000s 163.357us 0 1 0.00
aes_control_fi 2.000s 47.201us 1 1 100.00
aes_cipher_fi 18.000s 10017.271us 0 1 0.00
sec_cm_cipher_ctr_redun 0 1 0.00
aes_cipher_fi 18.000s 10017.271us 0 1 0.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 4.000s 163.357us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 4.000s 163.357us 0 1 0.00
aes_control_fi 2.000s 47.201us 1 1 100.00
aes_ctr_fi 2.000s 72.820us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 4.000s 163.357us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 4.000s 163.357us 0 1 0.00
aes_control_fi 2.000s 47.201us 1 1 100.00
aes_cipher_fi 18.000s 10017.271us 0 1 0.00
aes_ctr_fi 2.000s 72.820us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 125.976us 1 1 100.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 4.000s 163.357us 0 1 0.00
aes_control_fi 2.000s 47.201us 1 1 100.00
aes_cipher_fi 18.000s 10017.271us 0 1 0.00
aes_ctr_fi 2.000s 72.820us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 4.000s 163.357us 0 1 0.00
aes_control_fi 2.000s 47.201us 1 1 100.00
aes_cipher_fi 18.000s 10017.271us 0 1 0.00
aes_ctr_fi 2.000s 72.820us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 4.000s 163.357us 0 1 0.00
aes_control_fi 2.000s 47.201us 1 1 100.00
aes_ctr_fi 2.000s 72.820us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_ghash_fi 4.000s 116.234us 1 1 100.00
aes_fi 4.000s 163.357us 0 1 0.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 4.000s 163.357us 0 1 0.00
aes_control_fi 2.000s 47.201us 1 1 100.00
aes_cipher_fi 18.000s 10017.271us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 79.000s 11054.499us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 2 test runs
aes_reseed 15224414218087768288445385675286495611758212951063021459882866679983711568073 144181
UVM_INFO @ 4753646325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 1292437174677168764199689245878146649836144414374846656847011287288210758833 6382
UVM_INFO @ 47278667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 22002988428091178885541460010313128720269015137939459710349550794733192195959 11822
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 2
----| Expected corrupted: 0
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! 1 test run
aes_cipher_fi 45912866049370056074841330761806170926246665598890001770162481028894546771660 148
UVM_INFO @ 10017271139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 73040767368135538560139030088457854107632639047584395078566239100439971785732 2526
UVM_INFO @ 11054498932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---