Simulation Results: aes/gcm_unmasked

 
16/07/2026 19:40:29 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.65 %
  • code
  • 90.85 %
  • assert
  • 97.75 %
  • func
  • 62.35 %
  • block
  • 90.32 %
  • line
  • 92.11 %
  • branch
  • 82.52 %
  • toggle
  • 97.99 %
  • FSM
  • 90.78 %
Validation stages
V1
100.00%
V2
94.12%
V2S
81.25%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 58.880us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 73.612us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 101.373us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 3.000s 90.315us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 7.000s 1720.988us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 4.000s 824.881us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 75.042us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 3.000s 90.315us 1 1 100.00
aes_csr_aliasing 4.000s 824.881us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 73.612us 1 1 100.00
aes_config_error 3.000s 66.124us 1 1 100.00
aes_stress 3.000s 74.639us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 73.612us 1 1 100.00
aes_config_error 3.000s 66.124us 1 1 100.00
aes_stress 3.000s 74.639us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 74.639us 1 1 100.00
aes_b2b 3.000s 90.063us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 74.639us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 73.612us 1 1 100.00
aes_config_error 3.000s 66.124us 1 1 100.00
aes_stress 3.000s 74.639us 1 1 100.00
aes_alert_reset 1.000s 86.752us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 55.257us 1 1 100.00
aes_config_error 3.000s 66.124us 1 1 100.00
aes_alert_reset 1.000s 86.752us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 294.585us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 5.000s 324.491us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 1.000s 86.752us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 74.639us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 74.639us 1 1 100.00
aes_sideload 3.000s 157.711us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 110.738us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 6.000s 583.191us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 1.000s 74.051us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 84.094us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 84.094us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 101.373us 1 1 100.00
aes_csr_rw 3.000s 90.315us 1 1 100.00
aes_csr_aliasing 4.000s 824.881us 1 1 100.00
aes_same_csr_outstanding 2.000s 63.390us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 101.373us 1 1 100.00
aes_csr_rw 3.000s 90.315us 1 1 100.00
aes_csr_aliasing 4.000s 824.881us 1 1 100.00
aes_same_csr_outstanding 2.000s 63.390us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 3.000s 63.822us 0 1 0.00
fault_inject 1 3 33.33
aes_fi 306.000s 200000.000us 0 1 0.00
aes_control_fi 27.000s 10002.686us 0 1 0.00
aes_cipher_fi 2.000s 51.319us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 109.768us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 109.768us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 109.768us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 109.768us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 222.866us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 2841.614us 1 1 100.00
aes_tl_intg_err 3.000s 218.903us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 218.903us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 1.000s 86.752us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 109.768us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 109.768us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 73.612us 1 1 100.00
aes_stress 3.000s 74.639us 1 1 100.00
aes_alert_reset 1.000s 86.752us 1 1 100.00
aes_core_fi 3.000s 126.373us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 66.124us 1 1 100.00
aes_stress 3.000s 74.639us 1 1 100.00
aes_core_fi 3.000s 126.373us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 109.768us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 66.549us 1 1 100.00
aes_stress 3.000s 74.639us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 74.639us 1 1 100.00
aes_sideload 3.000s 157.711us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 66.549us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 66.549us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 66.549us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 66.549us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 66.549us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 74.639us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 74.639us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 306.000s 200000.000us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 306.000s 200000.000us 0 1 0.00
aes_control_fi 27.000s 10002.686us 0 1 0.00
aes_cipher_fi 2.000s 51.319us 1 1 100.00
aes_ctr_fi 2.000s 54.289us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 306.000s 200000.000us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 306.000s 200000.000us 0 1 0.00
aes_control_fi 27.000s 10002.686us 0 1 0.00
aes_cipher_fi 2.000s 51.319us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 51.319us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 306.000s 200000.000us 0 1 0.00
sec_cm_ctr_fsm_redun 1 3 33.33
aes_fi 306.000s 200000.000us 0 1 0.00
aes_control_fi 27.000s 10002.686us 0 1 0.00
aes_ctr_fi 2.000s 54.289us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 306.000s 200000.000us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 306.000s 200000.000us 0 1 0.00
aes_control_fi 27.000s 10002.686us 0 1 0.00
aes_cipher_fi 2.000s 51.319us 1 1 100.00
aes_ctr_fi 2.000s 54.289us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 1.000s 86.752us 1 1 100.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 306.000s 200000.000us 0 1 0.00
aes_control_fi 27.000s 10002.686us 0 1 0.00
aes_cipher_fi 2.000s 51.319us 1 1 100.00
aes_ctr_fi 2.000s 54.289us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 306.000s 200000.000us 0 1 0.00
aes_control_fi 27.000s 10002.686us 0 1 0.00
aes_cipher_fi 2.000s 51.319us 1 1 100.00
aes_ctr_fi 2.000s 54.289us 1 1 100.00
sec_cm_ctr_fsm_local_esc 1 3 33.33
aes_fi 306.000s 200000.000us 0 1 0.00
aes_control_fi 27.000s 10002.686us 0 1 0.00
aes_ctr_fi 2.000s 54.289us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 306.000s 200000.000us 0 1 0.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 306.000s 200000.000us 0 1 0.00
aes_control_fi 27.000s 10002.686us 0 1 0.00
aes_cipher_fi 2.000s 51.319us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 8.000s 408.569us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 3 test runs
aes_reseed 30022806494405079119119386587782551116957218496945961351952670701693168401270 4416
UVM_INFO @ 63822190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 103312057118223250736715317635226376512140672226263778233456614231359734086334 32323
UVM_INFO @ 583191370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 15718875344856347833015427925610243743911680022546902577967000123428553547734 478
UVM_INFO @ 408569207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
aes_fi 13748727460974775853502821007102316799622676957118319555554024615103671700117 2728363
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! 1 test run
aes_control_fi 60584065958685901055946842650611738377770838418285808641854446048319844480045 146
UVM_INFO @ 10002685699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---