Simulation Results: alert_handler

 
16/07/2026 19:40:29 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.30 %
  • code
  • 91.30 %
  • assert
  • 98.47 %
  • func
  • 81.14 %
  • line
  • 99.70 %
  • branch
  • 98.54 %
  • cond
  • 92.19 %
  • toggle
  • 91.90 %
  • FSM
  • 74.19 %
Validation stages
V1
100.00%
V2
89.47%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 30.680s 1043.099us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 4.920s 85.014us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 4.690s 89.880us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 114.350s 3642.755us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 108.200s 8454.474us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 4.840s 287.012us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 4.690s 89.880us 1 1 100.00
alert_handler_csr_aliasing 108.200s 8454.474us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 31.150s 1837.252us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 29.980s 3980.906us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 2866.450s 741113.538us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 21.700s 463.044us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 30.680s 1043.099us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 7.540s 560.142us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 33.120s 3726.140us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 279.670s 38881.627us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 2018.230s 55242.755us 1 1 100.00
alert_handler_lpg_stub_clk 2336.010s 62092.880us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 2089.680s 116167.009us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 20.940s 681.793us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.670s 95.619us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.330s 6.319us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 5.810s 73.348us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 5.810s 73.348us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 4.920s 85.014us 1 1 100.00
alert_handler_csr_rw 4.690s 89.880us 1 1 100.00
alert_handler_csr_aliasing 108.200s 8454.474us 1 1 100.00
alert_handler_same_csr_outstanding 9.460s 105.591us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 4.920s 85.014us 1 1 100.00
alert_handler_csr_rw 4.690s 89.880us 1 1 100.00
alert_handler_csr_aliasing 108.200s 8454.474us 1 1 100.00
alert_handler_same_csr_outstanding 9.460s 105.591us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 149.590s 9888.011us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 149.590s 9888.011us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 149.590s 9888.011us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 149.590s 9888.011us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 960.470s 70109.587us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 10.910s 1374.564us 1 1 100.00
alert_handler_tl_intg_err 31.840s 2806.723us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 31.840s 2806.723us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 149.590s 9888.011us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 30.680s 1043.099us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 30.680s 1043.099us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 30.680s 1043.099us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 30.680s 1043.099us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 21.700s 463.044us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 2018.230s 55242.755us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 21.700s 463.044us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 2866.450s 741113.538us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 2866.450s 741113.538us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 10.910s 1374.564us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 10.910s 1374.564us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 10.910s 1374.564us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 10.910s 1374.564us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 10.910s 1374.564us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 10.910s 1374.564us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 10.910s 1374.564us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 10.910s 1374.564us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 10.910s 1374.564us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 37.680s 902.815us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state 1 test run
alert_handler_ping_timeout 27252719756597518684973550549764801968583071371878686153655979843652542380467 138
UVM_INFO @ 38881626998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 84531047067533106228068001507495998861789118690828492858811561771245650078350 194
UVM_INFO @ 681792695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 41306738558387150881095686290705477108223955711113161626604355205855970397083 102
UVM_INFO @ 902814550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---