Simulation Results: clkmgr

 
16/07/2026 19:40:29 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 75.07 %
  • code
  • 68.21 %
  • assert
  • 89.26 %
  • func
  • 67.75 %
  • line
  • 81.61 %
  • branch
  • 86.30 %
  • cond
  • 77.21 %
  • toggle
  • 95.94 %
  • FSM
  • 0.00 %
Validation stages
V1
50.00%
V2
61.54%
V2S
37.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 2.400s 214.007us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.080s 47.867us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.830s 18.035us 1 1 100.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 0.780s 16.546us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.880s 20.229us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 1.000s 24.435us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 1 2 50.00
clkmgr_csr_rw 0.830s 18.035us 1 1 100.00
clkmgr_csr_aliasing 0.880s 20.229us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.780s 22.657us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.670s 128.079us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.740s 14.702us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 2.400s 214.007us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.730s 15.000us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.660s 3.696us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.730s 15.000us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 0.690s 8.531us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 0.830s 18.569us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 6.680s 510.154us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 6.680s 510.154us 1 1 100.00
tl_d_outstanding_access 2 4 50.00
clkmgr_csr_hw_reset 1.080s 47.867us 1 1 100.00
clkmgr_csr_rw 0.830s 18.035us 1 1 100.00
clkmgr_csr_aliasing 0.880s 20.229us 0 1 0.00
clkmgr_same_csr_outstanding 0.720s 10.065us 0 1 0.00
tl_d_partial_access 2 4 50.00
clkmgr_csr_hw_reset 1.080s 47.867us 1 1 100.00
clkmgr_csr_rw 0.830s 18.035us 1 1 100.00
clkmgr_csr_aliasing 0.880s 20.229us 0 1 0.00
clkmgr_same_csr_outstanding 0.720s 10.065us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 87.610s 10036.625us 0 1 0.00
clkmgr_tl_intg_err 0.740s 11.253us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.550s 70.562us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.550s 70.562us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.550s 70.562us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.550s 70.562us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.730s 8.103us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.740s 11.253us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.730s 15.000us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.660s 3.696us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.550s 70.562us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.890s 26.099us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.830s 18.035us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 87.610s 10036.625us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.830s 18.035us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.830s 18.035us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 87.610s 10036.625us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.650s 3.964us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 1.540s 80.037us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 4 test runs
clkmgr_shadow_reg_errors_with_csr_rw 70842647266964623382213084121343290505966190574979103576847670736835587843380 75
UVM_INFO @ 8103063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 108875701305142277785921589259504834843370698332954201709020053080637672771650 104
UVM_INFO @ 11253327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_aliasing 97126490556823640216258261886831266303247954946715853303085532050849133434827 75
UVM_INFO @ 20229477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 85867350679706171604302145608749995940942830477001998599267163536057987811209 82
UVM_INFO @ 24434866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 3 test runs
clkmgr_frequency 60467516757443589856365676858995589652990810984919086124275365352077136326631 75
UVM_INFO @ 14999785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 106860582306915370289322534633291848979584838644305175337724097168761035986459 92
UVM_INFO @ 80037058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 64471547818014184212698664766891269701964400909851582768738661369895146654128 75
UVM_INFO @ 8530816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 1 test run
clkmgr_frequency_timeout 63942150758400290329055927593481017133044242731590689172414920800059390106817 78
UVM_INFO @ 3696042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en 1 test run
clkmgr_regwen 75499226846287315440181704572862268708932413889882374469837383908777457231320 74
UVM_INFO @ 3964298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 1 test run
clkmgr_sec_cm 38698235137803433935608318087961557048810165812629468046763221530522030864861 90
UVM_INFO @ 10036625286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 28631478047581411645436471429584047272718276674767572032039218009809555109229 75
UVM_INFO @ 16545874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 71959316295839079286791758835111941146267222684123159546649317989185345722059 75
UVM_INFO @ 10064682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---