Simulation Results: csrng

 
16/07/2026 19:40:29 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.81 %
  • code
  • 92.34 %
  • assert
  • 93.23 %
  • func
  • 71.86 %
  • block
  • 97.05 %
  • line
  • 97.73 %
  • branch
  • 92.68 %
  • toggle
  • 93.24 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 26.550us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 25.228us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 65.714us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 16.000s 1159.817us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 6.000s 338.101us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 3.000s 18.128us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 65.714us 1 1 100.00
csrng_csr_aliasing 6.000s 338.101us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 11.000s 1130.561us 1 1 100.00
alerts 1 1 100.00
csrng_alert 11.000s 530.723us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 28.015us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 3.000s 60.237us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 3.000s 60.237us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 79.000s 5299.357us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 50.126us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 61.584us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 6.000s 107.675us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 6.000s 107.675us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 25.228us 1 1 100.00
csrng_csr_rw 2.000s 65.714us 1 1 100.00
csrng_csr_aliasing 6.000s 338.101us 1 1 100.00
csrng_same_csr_outstanding 2.000s 95.353us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 25.228us 1 1 100.00
csrng_csr_rw 2.000s 65.714us 1 1 100.00
csrng_csr_aliasing 6.000s 338.101us 1 1 100.00
csrng_same_csr_outstanding 2.000s 95.353us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 5.000s 115.264us 1 1 100.00
csrng_tl_intg_err 4.000s 118.547us 1 1 100.00
sec_cm_config_regwen 1 2 50.00
csrng_regwen 2.000s 1.454us 0 1 0.00
csrng_csr_rw 2.000s 65.714us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 11.000s 530.723us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 79.000s 5299.357us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 11.000s 1130.561us 1 1 100.00
csrng_err 2.000s 28.015us 1 1 100.00
csrng_sec_cm 5.000s 115.264us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 11.000s 1130.561us 1 1 100.00
csrng_err 2.000s 28.015us 1 1 100.00
csrng_sec_cm 5.000s 115.264us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 11.000s 1130.561us 1 1 100.00
csrng_err 2.000s 28.015us 1 1 100.00
csrng_sec_cm 5.000s 115.264us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 11.000s 1130.561us 1 1 100.00
csrng_err 2.000s 28.015us 1 1 100.00
csrng_sec_cm 5.000s 115.264us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 11.000s 1130.561us 1 1 100.00
csrng_err 2.000s 28.015us 1 1 100.00
csrng_sec_cm 5.000s 115.264us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 11.000s 530.723us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 11.000s 1130.561us 1 1 100.00
csrng_err 2.000s 28.015us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 79.000s 5299.357us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 11.000s 530.723us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 4.000s 118.547us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 11.000s 1130.561us 1 1 100.00
csrng_err 2.000s 28.015us 1 1 100.00
csrng_sec_cm 5.000s 115.264us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 11.000s 1130.561us 1 1 100.00
csrng_err 2.000s 28.015us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 11.000s 1130.561us 1 1 100.00
csrng_err 2.000s 28.015us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 11.000s 1130.561us 1 1 100.00
csrng_err 2.000s 28.015us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 11.000s 1130.561us 1 1 100.00
csrng_err 2.000s 28.015us 1 1 100.00
csrng_sec_cm 5.000s 115.264us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 11.000s 1130.561us 1 1 100.00
csrng_err 2.000s 28.015us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 51.000s 2255.641us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 32336238559958313853577204669961771778824166151136280119399165927402668301079 100
UVM_INFO @ 60237426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE 1 test run
csrng_regwen 4393034600630024105416577312712708833005646120576787806940734944048739417706 99
UVM_INFO @ 1453916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_env_cfg.sv:348) [cfg] Check failed csr_reseed_counter == reseed_counter[app] (* [*] vs * [*]) 1 test run
csrng_stress_all_with_rand_reset 56413284029952436723344580560029635084541923259091050119369308999341279515124 175
UVM_INFO @ 2255640592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---