Simulation Results: dma

 
16/07/2026 19:40:29 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.49 %
  • code
  • 90.38 %
  • assert
  • 96.61 %
  • func
  • 60.47 %
  • block
  • 97.34 %
  • line
  • 96.85 %
  • branch
  • 95.76 %
  • toggle
  • 77.37 %
  • FSM
  • 91.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 5.000s 1142.861us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 5.000s 4021.970us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 4.000s 237.152us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 2.000s 32.681us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 1.000s 78.069us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 7.000s 4448.650us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 6.000s 4336.122us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 134.057us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 1.000s 78.069us 1 1 100.00
dma_csr_aliasing 6.000s 4336.122us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 45.000s 3749.693us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 540.000s 92935.064us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 195.000s 85671.440us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 195.000s 85671.440us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 540.000s 92935.064us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 61.000s 5059.186us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 195.000s 85671.440us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 7.000s 2306.994us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 116.000s 45992.235us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 2.000s 72.159us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 2.000s 26.208us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 3.000s 893.320us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 3.000s 893.320us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 2.000s 32.681us 1 1 100.00
dma_csr_rw 1.000s 78.069us 1 1 100.00
dma_csr_aliasing 6.000s 4336.122us 1 1 100.00
dma_same_csr_outstanding 2.000s 122.155us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 2.000s 32.681us 1 1 100.00
dma_csr_rw 1.000s 78.069us 1 1 100.00
dma_csr_aliasing 6.000s 4336.122us 1 1 100.00
dma_same_csr_outstanding 2.000s 122.155us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 13.000s 340.766us 1 1 100.00
dma_generic_stress 61.000s 5059.186us 1 1 100.00
dma_handshake_stress 195.000s 85671.440us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 8.000s 1246.109us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 4.000s 92.885us 1 1 100.00
dma_sec_cm 2.000s 22.967us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 90.000s 25502.586us 1 1 100.00
dma_longer_transfer 3.000s 339.484us 1 1 100.00
dma_stress_all_with_rand_reset 2.000s 105.570us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1287) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 103822715596783580144652962263690031780111424781267594166224423148939006034538 92
UVM_INFO @ 105569943ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---