Simulation Results: edn/edn0

 
16/07/2026 19:40:29 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 76.21 %
  • code
  • 84.76 %
  • assert
  • 94.91 %
  • func
  • 48.95 %
  • block
  • 94.29 %
  • line
  • 97.12 %
  • branch
  • 87.72 %
  • toggle
  • 70.49 %
  • FSM
  • 83.72 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 2.000s 29.358us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 2.000s 15.317us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.000s 25.704us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.000s 169.188us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 2.000s 50.624us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 2.000s 43.744us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.000s 25.704us 1 1 100.00
edn_csr_aliasing 2.000s 50.624us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.000s 60.589us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.000s 60.589us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.000s 60.589us 1 1 100.00
interrupts 1 1 100.00
edn_intr 2.000s 23.161us 1 1 100.00
alerts 1 1 100.00
edn_alert 2.000s 29.450us 1 1 100.00
errs 1 1 100.00
edn_err 1.000s 23.688us 1 1 100.00
disable 2 2 100.00
edn_disable 1.000s 20.998us 1 1 100.00
edn_disable_auto_req_mode 1.000s 42.797us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.000s 143.717us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 2.000s 14.587us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 3.000s 14.061us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.000s 139.598us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.000s 139.598us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 2.000s 15.317us 1 1 100.00
edn_csr_rw 1.000s 25.704us 1 1 100.00
edn_csr_aliasing 2.000s 50.624us 1 1 100.00
edn_same_csr_outstanding 1.000s 17.125us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 2.000s 15.317us 1 1 100.00
edn_csr_rw 1.000s 25.704us 1 1 100.00
edn_csr_aliasing 2.000s 50.624us 1 1 100.00
edn_same_csr_outstanding 1.000s 17.125us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 7.000s 10620.814us 1 1 100.00
edn_tl_intg_err 2.000s 54.712us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 2.000s 41.380us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 2.000s 29.450us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.000s 10620.814us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.000s 10620.814us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 7.000s 10620.814us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 7.000s 10620.814us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 2.000s 29.450us 1 1 100.00
edn_sec_cm 7.000s 10620.814us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 2.000s 29.450us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.000s 54.712us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 68.000s 4154.266us 1 1 100.00