Simulation Results: edn/edn1

 
16/07/2026 19:40:29 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.73 %
  • code
  • 85.17 %
  • assert
  • 98.18 %
  • func
  • 79.83 %
  • line
  • 98.33 %
  • branch
  • 93.72 %
  • cond
  • 89.23 %
  • toggle
  • 95.70 %
  • FSM
  • 48.86 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.010s 17.109us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.090s 19.749us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.720s 83.694us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.000s 993.273us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.930s 24.994us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.230s 105.220us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.720s 83.694us 1 1 100.00
edn_csr_aliasing 0.930s 24.994us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.970s 55.096us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.970s 55.096us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.970s 55.096us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.080s 20.665us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.020s 49.680us 1 1 100.00
errs 1 1 100.00
edn_err 1.050s 24.108us 1 1 100.00
disable 2 2 100.00
edn_disable 0.750s 22.820us 1 1 100.00
edn_disable_auto_req_mode 0.990s 228.898us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.130s 597.933us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.800s 25.393us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.850s 18.439us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.540s 211.918us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.540s 211.918us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.090s 19.749us 1 1 100.00
edn_csr_rw 0.720s 83.694us 1 1 100.00
edn_csr_aliasing 0.930s 24.994us 1 1 100.00
edn_same_csr_outstanding 1.090s 19.402us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.090s 19.749us 1 1 100.00
edn_csr_rw 0.720s 83.694us 1 1 100.00
edn_csr_aliasing 0.930s 24.994us 1 1 100.00
edn_same_csr_outstanding 1.090s 19.402us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.510s 405.125us 1 1 100.00
edn_tl_intg_err 1.750s 174.417us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.960s 47.869us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.020s 49.680us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.510s 405.125us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.510s 405.125us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.510s 405.125us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.510s 405.125us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.020s 49.680us 1 1 100.00
edn_sec_cm 2.510s 405.125us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.020s 49.680us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.750s 174.417us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 35.140s 5452.096us 1 1 100.00