Simulation Results: hmac

 
16/07/2026 19:40:29 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 74.05 %
  • code
  • 95.91 %
  • assert
  • 97.17 %
  • func
  • 29.06 %
  • block
  • 97.41 %
  • line
  • 98.35 %
  • branch
  • 93.52 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 3.000s 168.067us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.000s 47.434us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 2.000s 256.572us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 10.000s 1280.249us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 4.000s 1488.330us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 696.000s 1380002.326us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 2.000s 256.572us 1 1 100.00
hmac_csr_aliasing 4.000s 1488.330us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 40.000s 1178.603us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 44.000s 1329.707us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 10.000s 262.843us 1 1 100.00
hmac_test_sha384_vectors 22.000s 319.644us 1 1 100.00
hmac_test_sha512_vectors 24.000s 357.037us 1 1 100.00
hmac_test_hmac256_vectors 11.000s 373.251us 1 1 100.00
hmac_test_hmac384_vectors 15.000s 476.680us 1 1 100.00
hmac_test_hmac512_vectors 15.000s 976.543us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 19.000s 22114.525us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 189.000s 5863.028us 1 1 100.00
error 1 1 100.00
hmac_error 21.000s 475.166us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 36.000s 8346.818us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 3.000s 168.067us 1 1 100.00
hmac_long_msg 40.000s 1178.603us 1 1 100.00
hmac_back_pressure 44.000s 1329.707us 1 1 100.00
hmac_datapath_stress 189.000s 5863.028us 1 1 100.00
hmac_burst_wr 19.000s 22114.525us 1 1 100.00
hmac_stress_all 25.000s 1009.012us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 3.000s 168.067us 1 1 100.00
hmac_long_msg 40.000s 1178.603us 1 1 100.00
hmac_back_pressure 44.000s 1329.707us 1 1 100.00
hmac_datapath_stress 189.000s 5863.028us 1 1 100.00
hmac_wipe_secret 36.000s 8346.818us 1 1 100.00
hmac_test_sha256_vectors 10.000s 262.843us 1 1 100.00
hmac_test_sha384_vectors 22.000s 319.644us 1 1 100.00
hmac_test_sha512_vectors 24.000s 357.037us 1 1 100.00
hmac_test_hmac256_vectors 11.000s 373.251us 1 1 100.00
hmac_test_hmac384_vectors 15.000s 476.680us 1 1 100.00
hmac_test_hmac512_vectors 15.000s 976.543us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 3.000s 168.067us 1 1 100.00
hmac_long_msg 40.000s 1178.603us 1 1 100.00
hmac_back_pressure 44.000s 1329.707us 1 1 100.00
hmac_datapath_stress 189.000s 5863.028us 1 1 100.00
hmac_burst_wr 19.000s 22114.525us 1 1 100.00
hmac_error 21.000s 475.166us 1 1 100.00
hmac_wipe_secret 36.000s 8346.818us 1 1 100.00
hmac_test_sha256_vectors 10.000s 262.843us 1 1 100.00
hmac_test_sha384_vectors 22.000s 319.644us 1 1 100.00
hmac_test_sha512_vectors 24.000s 357.037us 1 1 100.00
hmac_test_hmac256_vectors 11.000s 373.251us 1 1 100.00
hmac_test_hmac384_vectors 15.000s 476.680us 1 1 100.00
hmac_test_hmac512_vectors 15.000s 976.543us 1 1 100.00
hmac_stress_all 25.000s 1009.012us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 25.000s 1009.012us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 1.000s 13.034us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 1.000s 40.463us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.000s 714.923us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.000s 714.923us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.000s 47.434us 1 1 100.00
hmac_csr_rw 2.000s 256.572us 1 1 100.00
hmac_csr_aliasing 4.000s 1488.330us 1 1 100.00
hmac_same_csr_outstanding 2.000s 172.948us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.000s 47.434us 1 1 100.00
hmac_csr_rw 2.000s 256.572us 1 1 100.00
hmac_csr_aliasing 4.000s 1488.330us 1 1 100.00
hmac_same_csr_outstanding 2.000s 172.948us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.000s 129.578us 1 1 100.00
hmac_tl_intg_err 3.000s 423.426us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.000s 423.426us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 3.000s 168.067us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.000s 57.198us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 78.000s 5599.510us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.000s 20.858us 1 1 100.00