Simulation Results

Simulation Results: i2c

16/07/2026 19:40:29 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
87.58 %

code
85.66 %

assert
97.67 %

func
79.41 %

block
95.98 %

line
95.32 %

branch
92.79 %

toggle
72.52 %

FSM
82.01 %

Validation stages

V1		100.00%
V2		82.93%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	48.000s	1182.987us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	12.000s	5625.353us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	2.000s	49.300us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	1.000s	19.898us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	3.000s	335.434us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	3.000s	106.675us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.000s	37.543us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	1.000s	19.898us	1	1	100.00
	i2c_csr_aliasing	3.000s	106.675us	1	1	100.00

34/41 passed

82.93 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				1	1	100.00
	i2c_host_error_intr	3.000s	104.585us	1	1	100.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	3601.000s	0.000us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	19.000s	12563.393us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	1.000s	45.869us	1	1	100.00
host_fifo_watermark				0	1	0.00
	i2c_host_fifo_watermark	3602.088s	0.000us	0	1	0.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	1421.000s	9077.945us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	2.000s	827.209us	1	1	100.00
	i2c_host_fifo_fmt_empty	35.000s	2325.363us	1	1	100.00
	i2c_host_fifo_reset_rx	11.000s	920.723us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	272.000s	2163.267us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	10.000s	2769.984us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	2.000s	91.633us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	3.000s	2315.498us	0	1	0.00
target_stress_all				0	1	0.00
	i2c_target_stress_all	3600.000s	0.000us	0	1	0.00
target_maxperf				1	1	100.00
	i2c_target_perf	5.000s	8335.470us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	18.000s	1173.445us	1	1	100.00
	i2c_target_intr_smoke	5.000s	1457.990us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	2.000s	548.067us	1	1	100.00
	i2c_target_fifo_reset_tx	3.000s	218.937us	1	1	100.00
target_fifo_full				2	3	66.67
	i2c_target_stress_wr	10.000s	16757.165us	1	1	100.00
	i2c_target_stress_rd	18.000s	1173.445us	1	1	100.00
	i2c_target_intr_stress_wr	3601.000s	0.000us	0	1	0.00
target_timeout				1	1	100.00
	i2c_target_timeout	8.000s	2922.700us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	2.000s	397.557us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	7.000s	4423.171us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	11.000s	10650.815us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	3.000s	619.550us	1	1	100.00
	i2c_target_fifo_watermarks_tx	2.000s	129.294us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	19.000s	12563.393us	1	1	100.00
	i2c_host_perf_precise	814.000s	6330.204us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	10.000s	2769.984us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	2.000s	165.035us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	4.000s	936.753us	1	1	100.00
	i2c_target_nack_acqfull_addr	4.000s	576.171us	1	1	100.00
	i2c_target_nack_txstretch	3.000s	125.392us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	14.000s	1782.426us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	3.000s	2524.070us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	1.000s	53.084us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	1.000s	17.555us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	3.000s	626.285us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	3.000s	626.285us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	2.000s	49.300us	1	1	100.00
	i2c_csr_rw	1.000s	19.898us	1	1	100.00
	i2c_csr_aliasing	3.000s	106.675us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	27.364us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	2.000s	49.300us	1	1	100.00
	i2c_csr_rw	1.000s	19.898us	1	1	100.00
	i2c_csr_aliasing	3.000s	106.675us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	27.364us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	2.000s	305.125us	1	1	100.00
	i2c_sec_cm	1.000s	285.653us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	2.000s	305.125us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	8.000s	448.862us	1
target_error_intr				1
	i2c_target_unexp_stop	2.000s	607.399us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	15.000s	1497.792us	1

Error Messages

	Test	seed	line	log context
Job timed out after * minutes				4 test runs
	i2c_host_fifo_watermark	85779530024222757462132487387124904656141461573039568964394541506315570769015	None
	i2c_host_stress_all	55329557443653324006424685557161488141563929964110545946533179569208852277510	None
	i2c_target_intr_stress_wr	91521155290141312741594227159306612593100329732767679649342175532939469550925	None
	i2c_target_stress_all	106302731867930991267220731672738803749550900503891546213401347925541748799027	None
UVM_ERROR (cip_base_vseq.sv:1287) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	15421830043777560579701160354710382842259876408906885190019674073458882485799	95	UVM_INFO @ 448861970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	1697060535863084118983041549336924489263749397875847256111428399792697882234	98	UVM_INFO @ 1497792443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	109959270305644806406061624494820641529012893292651169585879137176152233236562	93	UVM_INFO @ 2315498344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	22413544130895885873313627172949197238163308933207611701615925867683238024613	87	UVM_INFO @ 607399493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	65487589721058246151878605112888179531363964219483288055061179237132406177576	88	UVM_INFO @ 10650815128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:629) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead				1 test run
	i2c_host_mode_toggle	87230448905560606102434635154012405205827905007025448290748246220977176278877	96	--> EXP: --------------------------------------------------- Name Type Size Value ---------------------------------------------------