Simulation Results: lc_ctrl/volatile_unlock_disabled

 
16/07/2026 19:40:29 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.01 %
  • code
  • 92.45 %
  • assert
  • 96.83 %
  • func
  • 83.76 %
  • block
  • 96.57 %
  • line
  • 97.23 %
  • branch
  • 91.26 %
  • toggle
  • 86.07 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 4.000s 175.314us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 31.052us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 14.303us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 288.933us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 17.581us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 32.333us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 14.303us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 17.581us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.000s 253.858us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 10.000s 1345.339us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 96.836us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.000s 203.853us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 5.000s 230.820us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 9.000s 922.564us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 5.000s 230.820us 1 1 100.00
lc_ctrl_prog_failure 3.000s 203.853us 1 1 100.00
lc_ctrl_errors 9.000s 922.564us 1 1 100.00
lc_ctrl_security_escalation 10.000s 1672.402us 1 1 100.00
lc_ctrl_jtag_state_failure 27.000s 1512.329us 1 1 100.00
lc_ctrl_jtag_prog_failure 7.000s 968.067us 1 1 100.00
lc_ctrl_jtag_errors 15.000s 1961.505us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 8.000s 474.453us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 1899.677us 1 1 100.00
lc_ctrl_jtag_prog_failure 7.000s 968.067us 1 1 100.00
lc_ctrl_jtag_errors 15.000s 1961.505us 1 1 100.00
lc_ctrl_jtag_access 3.000s 396.768us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 7.000s 2312.975us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 95.039us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 289.659us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 9.000s 3164.961us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 9.000s 552.894us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 181.530us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 188.126us 1 1 100.00
lc_ctrl_jtag_alert_test 3.000s 579.954us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 8.000s 2096.485us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 14.183us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 23.000s 2432.232us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 17.905us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 4.000s 151.478us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 4.000s 151.478us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 31.052us 1 1 100.00
lc_ctrl_csr_rw 2.000s 14.303us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 17.581us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.000s 28.764us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 31.052us 1 1 100.00
lc_ctrl_csr_rw 2.000s 14.303us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 17.581us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.000s 28.764us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 263.281us 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 125.566us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 125.566us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 10.000s 1345.339us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 230.820us 1 1 100.00
lc_ctrl_sec_cm 3.000s 263.281us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 230.820us 1 1 100.00
lc_ctrl_sec_cm 3.000s 263.281us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.000s 230.820us 1 1 100.00
lc_ctrl_sec_cm 3.000s 263.281us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.000s 230.820us 1 1 100.00
lc_ctrl_sec_cm 3.000s 263.281us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 230.820us 1 1 100.00
lc_ctrl_sec_cm 3.000s 263.281us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 230.820us 1 1 100.00
lc_ctrl_sec_cm 3.000s 263.281us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 230.820us 1 1 100.00
lc_ctrl_sec_cm 3.000s 263.281us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 5.000s 230.820us 1 1 100.00
lc_ctrl_sec_cm 3.000s 263.281us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 10.000s 1672.402us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.000s 253.858us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 1899.677us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.000s 2362.837us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.000s 2362.837us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.000s 334.208us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 2015.217us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 2015.217us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 12.000s 6327.024us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 114543785045502638063108677568377662500568362403913556711306805974117082588413 1869
UVM_INFO @ 6327023989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---