Simulation Results: lc_ctrl/volatile_unlock_enabled

 
16/07/2026 19:40:29 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.15 %
  • code
  • 93.63 %
  • assert
  • 96.83 %
  • func
  • 85.99 %
  • block
  • 96.98 %
  • line
  • 97.57 %
  • branch
  • 92.33 %
  • toggle
  • 86.99 %
  • FSM
  • 97.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 3.000s 179.177us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 22.236us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 58.062us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 3.000s 501.551us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 50.177us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.000s 24.595us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 58.062us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 50.177us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.000s 351.751us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.000s 2454.912us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 22.816us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.000s 172.404us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.000s 387.522us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.000s 2539.294us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.000s 387.522us 1 1 100.00
lc_ctrl_prog_failure 2.000s 172.404us 1 1 100.00
lc_ctrl_errors 5.000s 2539.294us 1 1 100.00
lc_ctrl_security_escalation 4.000s 215.457us 1 1 100.00
lc_ctrl_jtag_state_failure 12.000s 1397.558us 1 1 100.00
lc_ctrl_jtag_prog_failure 7.000s 1902.250us 1 1 100.00
lc_ctrl_jtag_errors 22.000s 3191.756us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 5.000s 233.676us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.000s 2070.759us 1 1 100.00
lc_ctrl_jtag_prog_failure 7.000s 1902.250us 1 1 100.00
lc_ctrl_jtag_errors 22.000s 3191.756us 1 1 100.00
lc_ctrl_jtag_access 10.000s 2057.148us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 14.000s 1125.395us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.000s 105.200us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 148.247us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 11.000s 758.949us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 16.000s 1015.026us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 45.392us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 550.960us 1 1 100.00
lc_ctrl_jtag_alert_test 3.000s 81.819us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 5.000s 171.153us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 16.070us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 16.000s 11606.382us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 210.864us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 940.197us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 940.197us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 22.236us 1 1 100.00
lc_ctrl_csr_rw 1.000s 58.062us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 50.177us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.000s 50.449us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 22.236us 1 1 100.00
lc_ctrl_csr_rw 1.000s 58.062us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 50.177us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.000s 50.449us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.000s 423.578us 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 175.486us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 175.486us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.000s 2454.912us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 387.522us 1 1 100.00
lc_ctrl_sec_cm 5.000s 423.578us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 387.522us 1 1 100.00
lc_ctrl_sec_cm 5.000s 423.578us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.000s 387.522us 1 1 100.00
lc_ctrl_sec_cm 5.000s 423.578us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.000s 387.522us 1 1 100.00
lc_ctrl_sec_cm 5.000s 423.578us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 387.522us 1 1 100.00
lc_ctrl_sec_cm 5.000s 423.578us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 387.522us 1 1 100.00
lc_ctrl_sec_cm 5.000s 423.578us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 387.522us 1 1 100.00
lc_ctrl_sec_cm 5.000s 423.578us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.000s 387.522us 1 1 100.00
lc_ctrl_sec_cm 5.000s 423.578us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.000s 215.457us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.000s 351.751us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.000s 2070.759us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.000s 6660.002us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.000s 6660.002us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.000s 3953.595us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 1679.469us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 1679.469us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 7.000s 3169.807us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 56631547030541501658348122315506943721657517927462666754322070774855231669253 610
UVM_INFO @ 3169807119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---