Simulation Results: mbx

 
16/07/2026 19:40:29 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.92 %
  • code
  • 87.55 %
  • assert
  • 96.96 %
  • func
  • 76.26 %
  • block
  • 95.61 %
  • line
  • 95.13 %
  • branch
  • 88.29 %
  • toggle
  • 79.23 %
Validation stages
V1
83.33%
V2
72.73%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 38.000s 23022.093us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 1.000s 17.601us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 1.000s 14.350us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 5.000s 4648.895us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 1.000s 55.908us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
mbx_csr_mem_rw_with_rand_reset 1.000s 3.655us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 1.000s 14.350us 1 1 100.00
mbx_csr_aliasing 1.000s 55.908us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 0 1 0.00
mbx_stress 7.000s 1230.918us 0 1 0.00
mbx_max_activity 0 1 0.00
mbx_stress_zero_delays 3.000s 83.091us 0 1 0.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 55.000s 3069.994us 1 1 100.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 8.000s 762.710us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 2.000s 47.664us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 2.000s 34.884us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 1.000s 2.054us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 1.000s 2.054us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 1.000s 17.601us 1 1 100.00
mbx_csr_rw 1.000s 14.350us 1 1 100.00
mbx_csr_aliasing 1.000s 55.908us 1 1 100.00
mbx_same_csr_outstanding 1.000s 72.200us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 1.000s 17.601us 1 1 100.00
mbx_csr_rw 1.000s 14.350us 1 1 100.00
mbx_csr_aliasing 1.000s 55.908us 1 1 100.00
mbx_same_csr_outstanding 1.000s 72.200us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_tl_intg_err 2.000s 296.521us 1 1 100.00
mbx_sec_cm 1.000s 20.084us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
mbx_tl_errors 27196254126189011177551290617261820698424576159820482648056303990597335213978 85
TL item was: req: (cip_tl_seq_item@17940) { a_addr: 'hd17064f4 a_data: 'h4da8f5cc a_mask: 'h0 a_size: 'h1 a_param: 'h0 a_source: 'hf2 a_opcode: 'h1 a_user: 'h240fb d_param: 'h0 d_source: 'hf2 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h10aa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 2054005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_csr_mem_rw_with_rand_reset 10172907454438698946701746238404686404415047050802045387321125218161788500611 86
TL item was: req: (cip_tl_seq_item@20569) { a_addr: 'hd688e7b0 a_data: 'h8d59c2ce a_mask: 'h1 a_size: 'h1 a_param: 'h0 a_source: 'h1c a_opcode: 'h1 a_user: 'h24429 d_param: 'h0 d_source: 'h1c d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h10aa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 3654533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched 1 test run
mbx_stress 110820090530105388432287640575079214955980230736674982491993165337840255577036 518
UVM_INFO @ 1230917870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register 1 test run
mbx_stress_zero_delays 66687409184228425825666324784071276127965862207012419341115970593823278026402 154
UVM_INFO @ 83090862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---