Simulation Results: otbn

 
16/07/2026 19:40:29 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.07 %
  • code
  • 86.25 %
  • assert
  • 90.35 %
  • func
  • 96.61 %
  • block
  • 99.24 %
  • line
  • 99.44 %
  • branch
  • 94.70 %
  • toggle
  • 84.67 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
92.86%
V2S
88.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 13.000s 56.740us 1 1 100.00
single_binary 1 1 100.00
otbn_single 6.000s 13.208us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 4.000s 49.032us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 4.000s 14.355us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 6.000s 78.461us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 6.000s 26.911us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 7.000s 144.808us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 4.000s 14.355us 1 1 100.00
otbn_csr_aliasing 6.000s 26.911us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 94.000s 25796.249us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 34.000s 632.822us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 45.000s 137.807us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 61.000s 169.376us 1 1 100.00
back_to_back 0 1 0.00
otbn_multi 7.000s 216.976us 0 1 0.00
stress_all 1 1 100.00
otbn_stress_all 76.000s 1339.586us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 13.000s 36.506us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 5.000s 26.149us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 8.000s 31.706us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 5.000s 62.038us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 6.000s 18.577us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 6.000s 98.591us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 6.000s 98.591us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 4.000s 49.032us 1 1 100.00
otbn_csr_rw 4.000s 14.355us 1 1 100.00
otbn_csr_aliasing 6.000s 26.911us 1 1 100.00
otbn_same_csr_outstanding 5.000s 20.482us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 4.000s 49.032us 1 1 100.00
otbn_csr_rw 4.000s 14.355us 1 1 100.00
otbn_csr_aliasing 6.000s 26.911us 1 1 100.00
otbn_same_csr_outstanding 5.000s 20.482us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 13.000s 61.582us 1 1 100.00
otbn_dmem_err 14.000s 37.930us 1 1 100.00
internal_integrity 2 4 50.00
otbn_alu_bignum_mod_err 10.000s 34.714us 0 1 0.00
otbn_controller_ispr_rdata_err 9.000s 18.198us 1 1 100.00
otbn_mac_bignum_acc_err 8.000s 61.413us 0 1 0.00
otbn_urnd_err 4.000s 29.242us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 7.000s 214.733us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 7.000s 23.677us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 5.000s 71.418us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 172.000s 8402.167us 1 1 100.00
otbn_tl_intg_err 10.000s 139.896us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 24.000s 92.673us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 172.000s 8402.167us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 172.000s 8402.167us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 13.000s 56.740us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 14.000s 37.930us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 13.000s 61.582us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 10.000s 139.896us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 13.000s 36.506us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 13.000s 61.582us 1 1 100.00
otbn_dmem_err 14.000s 37.930us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 26.149us 1 1 100.00
otbn_illegal_mem_acc 7.000s 214.733us 1 1 100.00
otbn_sec_cm 172.000s 8402.167us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 172.000s 8402.167us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 6.000s 13.208us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 13.000s 61.582us 1 1 100.00
otbn_dmem_err 14.000s 37.930us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 26.149us 1 1 100.00
otbn_illegal_mem_acc 7.000s 214.733us 1 1 100.00
otbn_sec_cm 172.000s 8402.167us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 172.000s 8402.167us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 13.000s 36.506us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 13.000s 61.582us 1 1 100.00
otbn_dmem_err 14.000s 37.930us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 26.149us 1 1 100.00
otbn_illegal_mem_acc 7.000s 214.733us 1 1 100.00
otbn_sec_cm 172.000s 8402.167us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 172.000s 8402.167us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 6.000s 13.208us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 7.000s 40.067us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 6.000s 12.961us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 35.000s 424.663us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 35.000s 424.663us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 7.000s 54.256us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 172.000s 8402.167us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 172.000s 8402.167us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 9.000s 65.475us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 172.000s 8402.167us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 172.000s 8402.167us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 9.000s 24.913us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 9.000s 24.913us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 4.000s 26.913us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 6.000s 13.208us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 6.000s 13.208us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 6.000s 13.208us 1 1 100.00
sec_cm_write_mem_integrity 0 1 0.00
otbn_multi 7.000s 216.976us 0 1 0.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 6.000s 13.208us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 6.000s 13.208us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 7.000s 16.214us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 6.000s 13.208us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 172.000s 8402.167us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 152.000s 806.168us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 67.945us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 2 test runs
otbn_alu_bignum_mod_err 78811860515052155231405695382804220960378933256137519958837465554982618957991 115
UVM_INFO @ 34713500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_mac_bignum_acc_err 26117078255832960201540172602863979660507986499769054767509161035925309876032 116
UVM_INFO @ 61413223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 1 test run
otbn_multi 43490147363760570197359183546930030023903128339184887579456895438558259069010 143
UVM_INFO @ 216976272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otbn_stress_all_with_rand_reset 604163585834102361883089874565109286223042213857321454735834242897170472642 177
UVM_INFO @ 806168492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---