Simulation Results: otp_ctrl

 
16/07/2026 19:40:29 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 74.62 %
  • code
  • 72.38 %
  • assert
  • 93.56 %
  • func
  • 57.91 %
  • line
  • 87.48 %
  • branch
  • 84.14 %
  • cond
  • 85.96 %
  • toggle
  • 68.40 %
  • FSM
  • 35.91 %
Validation stages
V1
88.89%
V2
65.00%
V2S
66.67%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.450s 837.882us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 7.480s 427.934us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.660s 143.944us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.760s 55.749us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 5.120s 979.415us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 4.000s 356.004us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
otp_ctrl_csr_mem_rw_with_rand_reset 1.800s 60.139us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.760s 55.749us 1 1 100.00
otp_ctrl_csr_aliasing 4.000s 356.004us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.330s 80.621us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.380s 55.814us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 113.160s 7746.181us 0 1 0.00
init_fail 0 1 0.00
otp_ctrl_init_fail 2.200s 63.137us 0 1 0.00
partition_check 0 2 0.00
otp_ctrl_background_chks 24.510s 9616.438us 0 1 0.00
otp_ctrl_check_fail 4.680s 2539.812us 0 1 0.00
regwen_during_otp_init 0 1 0.00
otp_ctrl_regwen 4.040s 224.211us 0 1 0.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 18.540s 1865.557us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 17.390s 1351.441us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 20.360s 10529.255us 1 1 100.00
otp_ctrl_parallel_lc_esc 24.690s 16072.887us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 30.640s 6223.730us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 13.070s 8538.885us 1 1 100.00
test_access 0 1 0.00
otp_ctrl_test_access 14.460s 3190.187us 0 1 0.00
stress_all 0 1 0.00
otp_ctrl_stress_all 55.360s 26388.657us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.470s 47.188us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.630s 81.548us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 4.160s 150.546us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 4.160s 150.546us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.660s 143.944us 1 1 100.00
otp_ctrl_csr_rw 1.760s 55.749us 1 1 100.00
otp_ctrl_csr_aliasing 4.000s 356.004us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.180s 259.033us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.660s 143.944us 1 1 100.00
otp_ctrl_csr_rw 1.760s 55.749us 1 1 100.00
otp_ctrl_csr_aliasing 4.000s 356.004us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.180s 259.033us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 257.640s 16742.720us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 257.640s 16742.720us 1 1 100.00
otp_ctrl_tl_intg_err 23.200s 3999.943us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 257.640s 16742.720us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 257.640s 16742.720us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 23.200s 3999.943us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 7.480s 427.934us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 7.480s 427.934us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 257.640s 16742.720us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 257.640s 16742.720us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 257.640s 16742.720us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 257.640s 16742.720us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 257.640s 16742.720us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 257.640s 16742.720us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 257.640s 16742.720us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 257.640s 16742.720us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 257.640s 16742.720us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 257.640s 16742.720us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 257.640s 16742.720us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 257.640s 16742.720us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 257.640s 16742.720us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 257.640s 16742.720us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 257.640s 16742.720us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 24.690s 16072.887us 1 1 100.00
otp_ctrl_sec_cm 257.640s 16742.720us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 24.690s 16072.887us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 24.690s 16072.887us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 24.690s 16072.887us 1 1 100.00
otp_ctrl_macro_errs 13.070s 8538.885us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 24.690s 16072.887us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 24.690s 16072.887us 1 1 100.00
otp_ctrl_sec_cm 257.640s 16742.720us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 24.690s 16072.887us 1 1 100.00
otp_ctrl_sec_cm 257.640s 16742.720us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 24.690s 16072.887us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 24.690s 16072.887us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 24.690s 16072.887us 1 1 100.00
otp_ctrl_macro_errs 13.070s 8538.885us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 24.690s 16072.887us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 24.690s 16072.887us 1 1 100.00
otp_ctrl_sec_cm 257.640s 16742.720us 1 1 100.00
sec_cm_part_data_reg_integrity 0 1 0.00
otp_ctrl_init_fail 2.200s 63.137us 0 1 0.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 4.680s 2539.812us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 18.540s 1865.557us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 18.540s 1865.557us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 18.540s 1865.557us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 18.540s 1865.557us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 18.540s 1865.557us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 7.480s 427.934us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 18.540s 1865.557us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 7.480s 427.934us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 257.640s 16742.720us 1 1 100.00
sec_cm_direct_access_config_regwen 0 1 0.00
otp_ctrl_regwen 4.040s 224.211us 0 1 0.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 7.480s 427.934us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 7.480s 427.934us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 13.070s 8538.885us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 65.650s 26174.812us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 19.040s 981.039us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 2 test runs
otp_ctrl_low_freq_read 66372251928589677110353699172860267929629159358069148125093301300456505355214 89
UVM_INFO @ 26174812030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 16288318071622719264156440869097387807811819675020765566566714409263110530279 90
UVM_INFO @ 26388657426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 2 test runs
otp_ctrl_init_fail 108874636456560299623882647507304976337172697638653059166026565395173487152727 967
UVM_INFO @ 63137314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_regwen 94373184122161143064009730519872186824975427752740370497494939769245148773317 3874
UVM_INFO @ 224210731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_partition_walk 107844598049502863906409894717072442161071907859912414949327295964231144475057 110183
UVM_INFO @ 7746181236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:671) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr 1 test run
otp_ctrl_background_chks 43456694827068121678189283809079231606832081018216839332349089869248863292004 14567
UVM_INFO @ 9616438049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 1 test run
otp_ctrl_check_fail 97026333364988770696502560868762014526810548887298723209883176348233222602291 1502
UVM_INFO @ 2539812129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:958) [scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (* [*] vs * [*]) reg name: status, compare_mask * 1 test run
otp_ctrl_test_access 69305730458733624173541647209708340854663932669744374628892875206124160539183 10820
UVM_INFO @ 3190186623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 1 test run
otp_ctrl_stress_all_with_rand_reset 40963846957376972455561900549991719166658264126684292142923193710329575955312 610
UVM_INFO @ 981038937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_csr_mem_rw_with_rand_reset 108160048420661235232369212618021901137756914961437513429368478758749191012714 91
UVM_INFO @ 60138731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---