Simulation Results: rstmgr

 
16/07/2026 19:40:29 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.13 %
  • code
  • 99.17 %
  • assert
  • 98.53 %
  • func
  • 96.69 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.52 %
  • toggle
  • 99.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.140s 73.378us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.230s 91.302us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.770s 37.096us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 4.050s 208.694us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 0.980s 38.249us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.130s 64.741us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.770s 37.096us 1 1 100.00
rstmgr_csr_aliasing 0.980s 38.249us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.500s 178.117us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 0.930s 38.714us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.080s 83.177us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 5.900s 702.758us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 5.900s 702.758us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 5.900s 702.758us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 5.900s 702.758us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 19.310s 3027.131us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.000s 51.179us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.680s 41.177us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.680s 41.177us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.230s 91.302us 1 1 100.00
rstmgr_csr_rw 0.770s 37.096us 1 1 100.00
rstmgr_csr_aliasing 0.980s 38.249us 1 1 100.00
rstmgr_same_csr_outstanding 1.370s 39.369us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.230s 91.302us 1 1 100.00
rstmgr_csr_rw 0.770s 37.096us 1 1 100.00
rstmgr_csr_aliasing 0.980s 38.249us 1 1 100.00
rstmgr_same_csr_outstanding 1.370s 39.369us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 15.710s 3462.881us 1 1 100.00
rstmgr_tl_intg_err 2.820s 343.842us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 15.710s 3462.881us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 15.710s 3462.881us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.820s 343.842us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.190s 55.944us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.270s 480.908us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.960s 292.084us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 15.710s 3462.881us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.770s 37.096us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.770s 37.096us 1 1 100.00