Simulation Results

Simulation Results: rv_dm/use_dmi_interface

16/07/2026 19:40:29 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
90.28 %

code
82.44 %

assert
96.59 %

func
91.80 %

block
92.41 %

line
92.74 %

branch
79.36 %

toggle
77.30 %

FSM
80.36 %

Validation stages

V1		96.30%
V2		73.91%
V2S		100.00%
V3		0.00%
unmapped		0.00%

26/27 passed

96.30 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	31.000s	2907.247us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	34.000s	590.169us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	30.000s	97.697us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	36.000s	9969.480us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	32.000s	314.671us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	36.000s	7525.923us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	33.000s	4818.219us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	73.000s	36331.487us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	47.000s	29752.573us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	32.000s	695.250us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	31.000s	234.552us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	30.000s	161.014us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	34.000s	189.720us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	34.000s	159.071us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	33.000s	1361.726us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	30.000s	153.965us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	31.000s	796.595us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	32.000s	695.250us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	31.000s	121.243us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	32.000s	445.658us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	30.000s	161.014us	1	1	100.00
rom_read_access				1	1	100.00
	rv_dm_rom_read_access	30.000s	189.466us	1	1	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	32.000s	433.284us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	33.000s	61.661us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	76.000s	12548.212us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	48.000s	1988.896us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	30.000s	121.354us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	48.000s	1988.896us	1	1	100.00
	rv_dm_csr_rw	33.000s	61.661us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	30.000s	94.856us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	31.000s	97.280us	1	1	100.00

17/23 passed

73.91 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	31.000s	2907.247us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	32.000s	135.944us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	32.000s	117.773us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	32.000s	117.495us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	33.000s	636.440us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	33.000s	2411.711us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	37.000s	5215.397us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	32.000s	4129.277us	0	1	0.00
sba_autoincrement				1	1	100.00
	rv_dm_autoincr_sba_tl_access	36.000s	21577.019us	1	1	100.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	30.000s	142.398us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	31.000s	841.034us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	34.000s	192.520us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	34.000s	55.583us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	34.000s	7503.195us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	40.000s	3704.458us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	31.000s	176.135us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	30.000s	2596.859us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	29.000s	64.058us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	33.000s	164.352us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	33.000s	164.352us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	48.000s	1988.896us	1	1	100.00
	rv_dm_csr_hw_reset	32.000s	433.284us	1	1	100.00
	rv_dm_csr_rw	33.000s	61.661us	1	1	100.00
	rv_dm_same_csr_outstanding	33.000s	176.765us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	48.000s	1988.896us	1	1	100.00
	rv_dm_csr_hw_reset	32.000s	433.284us	1	1	100.00
	rv_dm_csr_rw	33.000s	61.661us	1	1	100.00
	rv_dm_same_csr_outstanding	33.000s	176.765us	1	1	100.00

V2S

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	38.000s	1107.001us	1	1	100.00
	rv_dm_tl_intg_err	36.000s	2314.464us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	36.000s	2314.464us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	31.000s	841.034us	1	1	100.00
	rv_dm_debug_disabled	30.000s	38.038us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	31.000s	841.034us	1	1	100.00
	rv_dm_debug_disabled	30.000s	38.038us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	31.000s	2907.247us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	31.000s	539.058us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	29.000s	63.863us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	29.000s	63.863us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	31.000s	539.058us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	31.000s	194.678us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	259.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared:				2 test runs
	rv_dm_sba_tl_access	89099578123517734499931721693709881737068144834158085289965576993493173206637	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23869
	rv_dm_delayed_resp_sba_tl_access	62480901480117155421304280917475812925807601101605733003369475721883190178250	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23814
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				2 test runs
	rv_dm_mem_tl_access_resuming	74274931636944717171269640023623555354210175108593812028920065056450734428925	87	UVM_INFO @ 189720256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	51669234580226718601238894685534998746846700989839244454117621322512651024566	92	UVM_INFO @ 2596859140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				2 test runs
	rv_dm_jtag_dmi_debug_disabled	1516266574732992412197998224400556054244814542273032131106035615287053059090	87	UVM_INFO @ 142398151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	24000365243200888990847573445249837249163863442749951838116950040362133377789	97	UVM_INFO @ 194678159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				1 test run
	rv_dm_bad_sba_tl_access	17309373296007278918982790015399751415104914563357643740824136511007878412042	107	UVM_INFO @ 4129276979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				1 test run
	rv_dm_hart_unavail	100924098595705188851381919519307716582829783426637413553304340244698772594531	87	UVM_INFO @ 55583187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	rv_dm_scanmode	89483055274132914766564348349576363286133079555685826991433084536870025170330	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---