Simulation Results: rv_timer

 
16/07/2026 19:40:29 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.17 %
  • code
  • 95.40 %
  • assert
  • 96.52 %
  • func
  • 99.58 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 87.92 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 2.000s 723.467us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 119.585us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 1.000s 21.504us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 3.000s 92.218us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.000s 56.124us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 2.000s 94.972us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 1.000s 21.504us 1 1 100.00
rv_timer_csr_aliasing 1.000s 56.124us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 1.000s 832.701us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 2.000s 2875.685us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 4.000s 12501.512us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 4.000s 12501.512us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 5.000s 11415.457us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 1.000s 42.315us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 1.000s 39.404us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.000s 60.402us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.000s 60.402us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 119.585us 1 1 100.00
rv_timer_csr_rw 1.000s 21.504us 1 1 100.00
rv_timer_csr_aliasing 1.000s 56.124us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 555.103us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 119.585us 1 1 100.00
rv_timer_csr_rw 1.000s 21.504us 1 1 100.00
rv_timer_csr_aliasing 1.000s 56.124us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 555.103us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 1.000s 314.931us 1 1 100.00
rv_timer_tl_intg_err 1.000s 327.426us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.000s 327.426us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 3.000s 1638.752us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 1.000s 98.310us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 15.000s 7426.056us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 107974066407368196655717547059416019327494580195439745255405021255834374804083 87
UVM_INFO @ 1638751947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 4219775246702089117855103906260061411668486798057050630010642623625065407420 84
UVM_INFO @ 832700963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 85616196250128232507303187304821967062927843649141102056729527782450640691751 84
UVM_INFO @ 98310448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---