Simulation Results: sram_ctrl/main

 
16/07/2026 19:40:29 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.00 %
  • code
  • 94.92 %
  • assert
  • 96.87 %
  • func
  • 93.20 %
  • block
  • 95.03 %
  • line
  • 95.65 %
  • branch
  • 92.23 %
  • toggle
  • 91.79 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 1351.734us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 45.819us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 13.198us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 836.954us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 20.518us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 1424.846us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 13.198us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 20.518us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 129.000s 48346.114us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 111.000s 33235.391us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 27.000s 23108.625us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 117.000s 18730.170us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 161.000s 17685.366us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 28.000s 12867.344us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 30.000s 31157.412us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 17.000s 7593.757us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 5.000s 1463.855us 1 1 100.00
sram_ctrl_partial_access_b2b 178.000s 22409.884us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 4.000s 662.633us 0 1 0.00
sram_ctrl_throughput_w_partial_write 4.000s 4718.495us 0 1 0.00
sram_ctrl_throughput_w_readback 3.000s 2767.539us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 9.000s 8184.065us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 3363.672us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 115.000s 28792.985us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 17.036us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 388.858us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 388.858us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 45.819us 1 1 100.00
sram_ctrl_csr_rw 1.000s 13.198us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 20.518us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 17.041us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 45.819us 1 1 100.00
sram_ctrl_csr_rw 1.000s 13.198us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 20.518us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 17.041us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 12.000s 3872.851us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 714.296us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 460.251us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 714.296us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 460.251us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 8184.065us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 8184.065us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 13.198us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 17.000s 7593.757us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 17.000s 7593.757us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 17.000s 7593.757us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 30.000s 31157.412us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 683.257us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 12.000s 3872.851us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 6.000s 714.161us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 1351.734us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 1351.734us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 17.000s 7593.757us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 714.296us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 30.000s 31157.412us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 714.296us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 714.296us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 1351.734us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 714.296us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 14.000s 641.974us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 75361063297623879975614741549176618428872324380222484487060904378649885365589 86
UVM_INFO @ 662633177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 62160567719608492875925743619211056505589683801383564252912754823443125980931 86
UVM_INFO @ 4718494903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 6548529512589753311180381949850028157598715220787556529414879558647830222699 86
UVM_INFO @ 2767538692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---