Simulation Results: sram_ctrl/ret

 
16/07/2026 19:40:29 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 90.92 %
  • code
  • 82.28 %
  • assert
  • 98.08 %
  • func
  • 92.40 %
  • block
  • 93.76 %
  • line
  • 94.91 %
  • branch
  • 89.51 %
  • toggle
  • 78.03 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 146.992us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 17.294us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 11.289us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 59.785us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 55.286us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.000s 81.657us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 11.289us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 55.286us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 6.000s 859.553us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 3.000s 170.089us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 12.000s 1055.768us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 95.000s 4061.941us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 6.000s 576.460us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 14.000s 855.608us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 6.000s 1374.008us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 8.000s 1564.171us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 1.000s 118.414us 1 1 100.00
sram_ctrl_partial_access_b2b 156.000s 22291.126us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 2.000s 30.927us 0 1 0.00
sram_ctrl_throughput_w_partial_write 1.000s 31.894us 0 1 0.00
sram_ctrl_throughput_w_readback 2.000s 490.226us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 4.000s 1103.085us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 30.587us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 20.000s 2092.329us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 31.776us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 203.032us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 203.032us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 17.294us 1 1 100.00
sram_ctrl_csr_rw 1.000s 11.289us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 55.286us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 14.226us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 17.294us 1 1 100.00
sram_ctrl_csr_rw 1.000s 11.289us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 55.286us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 14.226us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 508.180us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 2.000s 221.506us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 580.158us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 2.000s 221.506us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 580.158us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 4.000s 1103.085us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 4.000s 1103.085us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 11.289us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 8.000s 1564.171us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 8.000s 1564.171us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 8.000s 1564.171us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 6.000s 1374.008us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 2.000s 40.170us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 508.180us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.000s 141.517us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 146.992us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 146.992us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 8.000s 1564.171us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 2.000s 221.506us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 6.000s 1374.008us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 2.000s 221.506us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 221.506us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 146.992us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 221.506us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 21.000s 2638.624us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 103004734749355601204692205662098329135787648185034093260091595510166679619625 86
UVM_INFO @ 30926588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 61417628312031274150988522578984458251427423960599325157767120598459144422533 86
UVM_INFO @ 31893709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 109034264149317412341603979987765582382842428753122408084757701087796997520352 86
UVM_INFO @ 490225597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---