Simulation Results: uart

 
16/07/2026 19:40:29 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.94 %
  • code
  • 77.55 %
  • assert
  • 98.56 %
  • func
  • 90.69 %
  • block
  • 98.58 %
  • line
  • 99.24 %
  • branch
  • 97.24 %
  • toggle
  • 88.74 %
  • FSM
  • 25.00 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 5.000s 5772.716us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 1.000s 15.578us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 1.000s 17.884us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.000s 147.137us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 1.000s 58.719us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.000s 31.507us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 1.000s 17.884us 1 1 100.00
uart_csr_aliasing 1.000s 58.719us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 100.000s 151134.924us 1 1 100.00
parity 2 2 100.00
uart_smoke 5.000s 5772.716us 1 1 100.00
uart_tx_rx 100.000s 151134.924us 1 1 100.00
parity_error 2 2 100.00
uart_intr 246.000s 258083.030us 1 1 100.00
uart_rx_parity_err 235.000s 209645.878us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 100.000s 151134.924us 1 1 100.00
uart_intr 246.000s 258083.030us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 25.000s 187262.234us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 15.000s 12685.459us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 114.000s 105138.300us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 246.000s 258083.030us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 246.000s 258083.030us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 246.000s 258083.030us 1 1 100.00
perf 1 1 100.00
uart_perf 165.000s 20872.032us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 5.000s 7440.915us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 5.000s 7440.915us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 4.000s 939.184us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 3.000s 5776.442us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 2.000s 123.800us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 4.000s 6578.904us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 531.000s 123409.453us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 183.000s 45101.551us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 1.000s 38.772us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 1.000s 15.766us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 2.000s 175.325us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 2.000s 175.325us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 1.000s 15.578us 1 1 100.00
uart_csr_rw 1.000s 17.884us 1 1 100.00
uart_csr_aliasing 1.000s 58.719us 1 1 100.00
uart_same_csr_outstanding 2.000s 31.042us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 1.000s 15.578us 1 1 100.00
uart_csr_rw 1.000s 17.884us 1 1 100.00
uart_csr_aliasing 1.000s 58.719us 1 1 100.00
uart_same_csr_outstanding 2.000s 31.042us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.000s 38.795us 1 1 100.00
uart_tl_intg_err 1.000s 1266.586us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.000s 1266.586us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 22.000s 1368.161us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:502) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_noise_filter 4138621687285127086791398579615358247107413333465821847729448596039666253789 83
UVM_ERROR @ 376884796 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 376895322 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 377042686 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2, clk_pulses: 0
UVM_ERROR @ 377063738 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty