Simulation Results: aes/gcm_masked

 
20/07/2026 20:41:39 DVSim: v1.49.12 sha: 54120d8 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.52 %
  • code
  • 95.14 %
  • assert
  • 98.43 %
  • func
  • 63.00 %
  • block
  • 95.77 %
  • line
  • 97.53 %
  • branch
  • 89.48 %
  • toggle
  • 98.05 %
  • FSM
  • 95.48 %
Validation stages
V1
100.00%
V2
94.74%
V2S
94.44%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 59.132us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 88.900us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 215.294us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 77.489us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 828.824us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 253.828us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 120.134us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 77.489us 1 1 100.00
aes_csr_aliasing 3.000s 253.828us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 88.900us 1 1 100.00
aes_config_error 2.000s 180.530us 1 1 100.00
aes_stress 7.000s 1191.675us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 88.900us 1 1 100.00
aes_config_error 2.000s 180.530us 1 1 100.00
aes_stress 7.000s 1191.675us 1 1 100.00
back2back 2 2 100.00
aes_stress 7.000s 1191.675us 1 1 100.00
aes_b2b 4.000s 262.501us 1 1 100.00
backpressure 1 1 100.00
aes_stress 7.000s 1191.675us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 88.900us 1 1 100.00
aes_config_error 2.000s 180.530us 1 1 100.00
aes_stress 7.000s 1191.675us 1 1 100.00
aes_alert_reset 2.000s 65.647us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 120.938us 1 1 100.00
aes_config_error 2.000s 180.530us 1 1 100.00
aes_alert_reset 2.000s 65.647us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 78.452us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 7.000s 2261.186us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 7.000s 607.870us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 65.647us 1 1 100.00
stress 1 1 100.00
aes_stress 7.000s 1191.675us 1 1 100.00
sideload 2 2 100.00
aes_stress 7.000s 1191.675us 1 1 100.00
aes_sideload 4.000s 132.316us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 126.135us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 35.000s 2281.455us 0 1 0.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 3.000s 84.300us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 111.885us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 366.528us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 366.528us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 215.294us 1 1 100.00
aes_csr_rw 1.000s 77.489us 1 1 100.00
aes_csr_aliasing 3.000s 253.828us 1 1 100.00
aes_same_csr_outstanding 2.000s 136.259us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 215.294us 1 1 100.00
aes_csr_rw 1.000s 77.489us 1 1 100.00
aes_csr_aliasing 3.000s 253.828us 1 1 100.00
aes_same_csr_outstanding 2.000s 136.259us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 41.000s 1928.396us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 3.000s 132.701us 0 1 0.00
aes_control_fi 2.000s 129.971us 1 1 100.00
aes_cipher_fi 3.000s 84.955us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 3.000s 238.917us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 3.000s 238.917us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 3.000s 238.917us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 3.000s 238.917us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 1087.553us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 2403.692us 1 1 100.00
aes_tl_intg_err 2.000s 304.169us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 304.169us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 65.647us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 238.917us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 238.917us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 88.900us 1 1 100.00
aes_stress 7.000s 1191.675us 1 1 100.00
aes_alert_reset 2.000s 65.647us 1 1 100.00
aes_core_fi 3.000s 126.070us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 3.000s 84.300us 1 1 100.00
aes_config_error 2.000s 180.530us 1 1 100.00
aes_stress 7.000s 1191.675us 1 1 100.00
aes_core_fi 3.000s 126.070us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 238.917us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 76.995us 1 1 100.00
aes_stress 7.000s 1191.675us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 7.000s 1191.675us 1 1 100.00
aes_sideload 4.000s 132.316us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 76.995us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 76.995us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 76.995us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 76.995us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 76.995us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 7.000s 1191.675us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 7.000s 1191.675us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3.000s 132.701us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 3.000s 132.701us 0 1 0.00
aes_control_fi 2.000s 129.971us 1 1 100.00
aes_cipher_fi 3.000s 84.955us 1 1 100.00
aes_ctr_fi 3.000s 70.184us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3.000s 132.701us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 3.000s 132.701us 0 1 0.00
aes_control_fi 2.000s 129.971us 1 1 100.00
aes_cipher_fi 3.000s 84.955us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 84.955us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3.000s 132.701us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3.000s 132.701us 0 1 0.00
aes_control_fi 2.000s 129.971us 1 1 100.00
aes_ctr_fi 3.000s 70.184us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3.000s 132.701us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 3.000s 132.701us 0 1 0.00
aes_control_fi 2.000s 129.971us 1 1 100.00
aes_cipher_fi 3.000s 84.955us 1 1 100.00
aes_ctr_fi 3.000s 70.184us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 65.647us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 3.000s 132.701us 0 1 0.00
aes_control_fi 2.000s 129.971us 1 1 100.00
aes_cipher_fi 3.000s 84.955us 1 1 100.00
aes_ctr_fi 3.000s 70.184us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 3.000s 132.701us 0 1 0.00
aes_control_fi 2.000s 129.971us 1 1 100.00
aes_cipher_fi 3.000s 84.955us 1 1 100.00
aes_ctr_fi 3.000s 70.184us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3.000s 132.701us 0 1 0.00
aes_control_fi 2.000s 129.971us 1 1 100.00
aes_ctr_fi 3.000s 70.184us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_ghash_fi 3.000s 139.679us 1 1 100.00
aes_fi 3.000s 132.701us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 3.000s 132.701us 0 1 0.00
aes_control_fi 2.000s 129.971us 1 1 100.00
aes_cipher_fi 3.000s 84.955us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 2.000s 36.094us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 2 test runs
aes_fi 31401436634127070193298648032637164750552745045737454655477705418565596868612 6852
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 2
----| Expected corrupted: 0
aes_stress_all 34992526627042940477342747498368425537682223670592974340744966918001615928093 128156
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 2
----| Seen: 1
----| Expected corrupted: 0
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 13735677844287069856040397464107166114707345023042666093341963414333338982546 170
UVM_INFO @ 36093703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---