Simulation Results: aes/gcm_unmasked

 
20/07/2026 20:41:39 DVSim: v1.49.12 sha: 54120d8 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.28 %
  • code
  • 90.37 %
  • assert
  • 97.75 %
  • func
  • 61.73 %
  • block
  • 90.35 %
  • line
  • 92.49 %
  • branch
  • 82.35 %
  • toggle
  • 97.99 %
  • FSM
  • 88.65 %
Validation stages
V1
100.00%
V2
94.12%
V2S
81.25%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 76.549us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 104.788us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 79.934us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 140.328us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 3.000s 510.490us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 157.028us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 65.280us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 140.328us 1 1 100.00
aes_csr_aliasing 2.000s 157.028us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 104.788us 1 1 100.00
aes_config_error 3.000s 249.526us 1 1 100.00
aes_stress 3.000s 535.080us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 104.788us 1 1 100.00
aes_config_error 3.000s 249.526us 1 1 100.00
aes_stress 3.000s 535.080us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 535.080us 1 1 100.00
aes_b2b 3.000s 145.654us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 535.080us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 2.000s 104.788us 1 1 100.00
aes_config_error 3.000s 249.526us 1 1 100.00
aes_stress 3.000s 535.080us 1 1 100.00
aes_alert_reset 3.000s 837.899us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 2.000s 83.644us 1 1 100.00
aes_config_error 3.000s 249.526us 1 1 100.00
aes_alert_reset 3.000s 837.899us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 71.252us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 3.000s 495.582us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 3.000s 837.899us 0 1 0.00
stress 1 1 100.00
aes_stress 3.000s 535.080us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 535.080us 1 1 100.00
aes_sideload 2.000s 136.074us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 64.267us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 5.000s 711.964us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 1.000s 107.705us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 243.327us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 243.327us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 79.934us 1 1 100.00
aes_csr_rw 2.000s 140.328us 1 1 100.00
aes_csr_aliasing 2.000s 157.028us 1 1 100.00
aes_same_csr_outstanding 2.000s 191.717us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 79.934us 1 1 100.00
aes_csr_rw 2.000s 140.328us 1 1 100.00
aes_csr_aliasing 2.000s 157.028us 1 1 100.00
aes_same_csr_outstanding 2.000s 191.717us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 2.000s 104.345us 0 1 0.00
fault_inject 2 3 66.67
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 2.000s 65.257us 1 1 100.00
aes_cipher_fi 2.000s 52.965us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 145.933us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 145.933us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 145.933us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 145.933us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 272.942us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 3677.161us 1 1 100.00
aes_tl_intg_err 2.000s 110.297us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 110.297us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 3.000s 837.899us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 145.933us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 145.933us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 2.000s 104.788us 1 1 100.00
aes_stress 3.000s 535.080us 1 1 100.00
aes_alert_reset 3.000s 837.899us 0 1 0.00
aes_core_fi 2.000s 140.101us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 249.526us 1 1 100.00
aes_stress 3.000s 535.080us 1 1 100.00
aes_core_fi 2.000s 140.101us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 145.933us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 1.000s 74.801us 1 1 100.00
aes_stress 3.000s 535.080us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 535.080us 1 1 100.00
aes_sideload 2.000s 136.074us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 1.000s 74.801us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 1.000s 74.801us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 1.000s 74.801us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 1.000s 74.801us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 1.000s 74.801us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 535.080us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 535.080us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3601.000s 0.000us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 2.000s 65.257us 1 1 100.00
aes_cipher_fi 2.000s 52.965us 1 1 100.00
aes_ctr_fi 2.000s 64.856us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3601.000s 0.000us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 2.000s 65.257us 1 1 100.00
aes_cipher_fi 2.000s 52.965us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 52.965us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3601.000s 0.000us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 2.000s 65.257us 1 1 100.00
aes_ctr_fi 2.000s 64.856us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3601.000s 0.000us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 2.000s 65.257us 1 1 100.00
aes_cipher_fi 2.000s 52.965us 1 1 100.00
aes_ctr_fi 2.000s 64.856us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 3.000s 837.899us 0 1 0.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 2.000s 65.257us 1 1 100.00
aes_cipher_fi 2.000s 52.965us 1 1 100.00
aes_ctr_fi 2.000s 64.856us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 2.000s 65.257us 1 1 100.00
aes_cipher_fi 2.000s 52.965us 1 1 100.00
aes_ctr_fi 2.000s 64.856us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 2.000s 65.257us 1 1 100.00
aes_ctr_fi 2.000s 64.856us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3601.000s 0.000us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 2.000s 65.257us 1 1 100.00
aes_cipher_fi 2.000s 52.965us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 1.000s 11.965us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:785) scoreboard [scoreboard] # * 1 test run
aes_alert_reset 48485767123432715956759810656305129583432365162272838552981760750972391482244 2108
TEST FAILED MESSAGES DID NOT MATCH
0 26 ca 00 0
1 00 f5 00 0
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_reseed 45732131309433770339084276430527085932916948901868839979182927503977940247424 1924
UVM_INFO @ 104344927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
aes_fi 62329386158552970712512137043007740146811892992453946095329171094460514436516 None
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 17633834189230372113509284388490249555396589437400646197148030193517870995680 163
UVM_INFO @ 11964801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---