Simulation Results: clkmgr

 
20/07/2026 20:41:39 DVSim: v1.49.12 sha: 54120d8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 75.90 %
  • code
  • 68.39 %
  • assert
  • 89.67 %
  • func
  • 69.65 %
  • line
  • 81.66 %
  • branch
  • 86.53 %
  • cond
  • 77.99 %
  • toggle
  • 95.75 %
  • FSM
  • 0.00 %
Validation stages
V1
33.33%
V2
61.54%
V2S
25.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.910s 18.716us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.290s 32.933us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.600s 4.236us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 1.940s 79.682us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.800s 12.906us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 0.790s 14.451us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
clkmgr_csr_rw 0.600s 4.236us 0 1 0.00
clkmgr_csr_aliasing 0.800s 12.906us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 1.010s 49.491us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 2.470s 127.640us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.710s 149.759us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.910s 18.716us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.670s 10.688us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.730s 3.517us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.670s 10.688us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 1.480s 103.155us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 1.180s 30.804us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 5.420s 443.666us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 5.420s 443.666us 1 1 100.00
tl_d_outstanding_access 2 4 50.00
clkmgr_csr_hw_reset 1.290s 32.933us 1 1 100.00
clkmgr_csr_rw 0.600s 4.236us 0 1 0.00
clkmgr_csr_aliasing 0.800s 12.906us 0 1 0.00
clkmgr_same_csr_outstanding 1.730s 137.481us 1 1 100.00
tl_d_partial_access 2 4 50.00
clkmgr_csr_hw_reset 1.290s 32.933us 1 1 100.00
clkmgr_csr_rw 0.600s 4.236us 0 1 0.00
clkmgr_csr_aliasing 0.800s 12.906us 0 1 0.00
clkmgr_same_csr_outstanding 1.730s 137.481us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 96.490s 10037.405us 0 1 0.00
clkmgr_tl_intg_err 1.300s 79.460us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.160s 55.674us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.160s 55.674us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.160s 55.674us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.160s 55.674us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 1.060s 25.745us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 1.300s 79.460us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.670s 10.688us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.730s 3.517us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.160s 55.674us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 2.310s 108.883us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.600s 4.236us 0 1 0.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 96.490s 10037.405us 0 1 0.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.600s 4.236us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.600s 4.236us 0 1 0.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 96.490s 10037.405us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.640s 3.609us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 1.000s 17.636us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 4 test runs
clkmgr_shadow_reg_errors_with_csr_rw 41578754732127150317539414757950669571558036145437731804575938552439348855595 75
UVM_INFO @ 25744632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 33810513356500817323446222198634675510579859524321465549552630687627476493650 109
UVM_INFO @ 79460464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_aliasing 107641082208919691993272762654541540447447015275114285551201423066089773899381 75
UVM_INFO @ 12905731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 114810229611994757426745259922755266810578967796850575451562859780360342718865 76
UVM_INFO @ 14450501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency 30325596105086271337485984023924065117860264475015202517484200597328223277742 75
UVM_INFO @ 10688488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 67437818277556458995806054629611295615325549770385341977446011888675976884063 87
UVM_INFO @ 103154826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency_timeout 76493214571167703704977817184068110976108961476282309992611117275338993612434 77
UVM_INFO @ 3516705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 43760187515219309345218082848182521186332767513998268648304703277277740416708 85
UVM_INFO @ 17636289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en 1 test run
clkmgr_regwen 61275792181862521087151064641907675833370561175954258287655132450880064530041 74
UVM_INFO @ 3609352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 1 test run
clkmgr_sec_cm 76436101622085650779772416711388308778416445169769036955095666742667641071167 109
UVM_INFO @ 10037404851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 1 test run
clkmgr_csr_rw 74146717710204524517624006842740256301476894990233399216865149722391993099870 75
UVM_INFO @ 4236359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 28679641946019701502165208152432545858417438019364418325243810649077618860925 75
UVM_INFO @ 79681509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---