Simulation Results: csrng

 
20/07/2026 20:41:39 DVSim: v1.49.12 sha: 54120d8 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.27 %
  • code
  • 92.38 %
  • assert
  • 93.89 %
  • func
  • 78.55 %
  • block
  • 97.05 %
  • line
  • 97.69 %
  • branch
  • 92.68 %
  • toggle
  • 93.44 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 3.000s 47.952us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 49.382us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 50.709us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 14.000s 670.529us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 3.000s 49.363us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 85.140us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 50.709us 1 1 100.00
csrng_csr_aliasing 3.000s 49.363us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 3.000s 64.347us 1 1 100.00
alerts 1 1 100.00
csrng_alert 9.000s 225.806us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 21.725us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 2557.000s 200000.000us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 2557.000s 200000.000us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 427.000s 16341.510us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 18.009us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 1.000s 26.402us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 3.000s 149.863us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 3.000s 149.863us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 49.382us 1 1 100.00
csrng_csr_rw 2.000s 50.709us 1 1 100.00
csrng_csr_aliasing 3.000s 49.363us 1 1 100.00
csrng_same_csr_outstanding 3.000s 43.824us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 49.382us 1 1 100.00
csrng_csr_rw 2.000s 50.709us 1 1 100.00
csrng_csr_aliasing 3.000s 49.363us 1 1 100.00
csrng_same_csr_outstanding 3.000s 43.824us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 3.000s 88.478us 1 1 100.00
csrng_tl_intg_err 3.000s 122.963us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 2.000s 24.951us 1 1 100.00
csrng_csr_rw 2.000s 50.709us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 9.000s 225.806us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 427.000s 16341.510us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 3.000s 64.347us 1 1 100.00
csrng_err 2.000s 21.725us 1 1 100.00
csrng_sec_cm 3.000s 88.478us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 3.000s 64.347us 1 1 100.00
csrng_err 2.000s 21.725us 1 1 100.00
csrng_sec_cm 3.000s 88.478us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 3.000s 64.347us 1 1 100.00
csrng_err 2.000s 21.725us 1 1 100.00
csrng_sec_cm 3.000s 88.478us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 3.000s 64.347us 1 1 100.00
csrng_err 2.000s 21.725us 1 1 100.00
csrng_sec_cm 3.000s 88.478us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 3.000s 64.347us 1 1 100.00
csrng_err 2.000s 21.725us 1 1 100.00
csrng_sec_cm 3.000s 88.478us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 9.000s 225.806us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 3.000s 64.347us 1 1 100.00
csrng_err 2.000s 21.725us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 427.000s 16341.510us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 9.000s 225.806us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 3.000s 122.963us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 3.000s 64.347us 1 1 100.00
csrng_err 2.000s 21.725us 1 1 100.00
csrng_sec_cm 3.000s 88.478us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 3.000s 64.347us 1 1 100.00
csrng_err 2.000s 21.725us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 3.000s 64.347us 1 1 100.00
csrng_err 2.000s 21.725us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 3.000s 64.347us 1 1 100.00
csrng_err 2.000s 21.725us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 3.000s 64.347us 1 1 100.00
csrng_err 2.000s 21.725us 1 1 100.00
csrng_sec_cm 3.000s 88.478us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 3.000s 64.347us 1 1 100.00
csrng_err 2.000s 21.725us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 3600.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
csrng_cmds 22072799598325450388128852251627167883288540763574000009200586158318747130870 109
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 106529572011568996958588008217632156970826324113837457534000483217000235191197 None