Simulation Results: dma

 
20/07/2026 20:41:39 DVSim: v1.49.12 sha: 54120d8 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 81.11 %
  • code
  • 90.38 %
  • assert
  • 95.97 %
  • func
  • 56.98 %
  • block
  • 97.34 %
  • line
  • 96.85 %
  • branch
  • 95.76 %
  • toggle
  • 77.37 %
  • FSM
  • 91.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 5.000s 390.315us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 5.000s 697.943us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 5.000s 1327.946us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 2.000s 74.772us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 1.000s 70.622us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 7.000s 3207.493us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 4.000s 1163.849us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 107.949us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 1.000s 70.622us 1 1 100.00
dma_csr_aliasing 4.000s 1163.849us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 31.000s 2556.846us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 81.000s 35728.153us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 1452.000s 2032135.410us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 1452.000s 2032135.410us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 81.000s 35728.153us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 71.000s 27743.719us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 1452.000s 2032135.410us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 18.000s 2920.789us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 30.000s 5259.420us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 38.906us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 30.049us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 2.000s 162.093us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 2.000s 162.093us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 2.000s 74.772us 1 1 100.00
dma_csr_rw 1.000s 70.622us 1 1 100.00
dma_csr_aliasing 4.000s 1163.849us 1 1 100.00
dma_same_csr_outstanding 2.000s 75.189us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 2.000s 74.772us 1 1 100.00
dma_csr_rw 1.000s 70.622us 1 1 100.00
dma_csr_aliasing 4.000s 1163.849us 1 1 100.00
dma_same_csr_outstanding 2.000s 75.189us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 14.000s 1221.507us 1 1 100.00
dma_generic_stress 71.000s 27743.719us 1 1 100.00
dma_handshake_stress 1452.000s 2032135.410us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 6.000s 332.168us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 3.000s 1678.858us 1 1 100.00
dma_sec_cm 2.000s 26.455us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 60.000s 7489.995us 1 1 100.00
dma_longer_transfer 3.000s 108.103us 1 1 100.00
dma_stress_all_with_rand_reset 12.000s 567.935us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1287) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 65359046436038094173729163401648468997299396902694079285461187343729610871868 105
UVM_INFO @ 567934603ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---