Simulation Results: edn/edn0

 
20/07/2026 20:41:39 DVSim: v1.49.12 sha: 54120d8 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 79.28 %
  • code
  • 90.81 %
  • assert
  • 98.23 %
  • func
  • 48.81 %
  • block
  • 95.99 %
  • line
  • 98.05 %
  • branch
  • 91.20 %
  • toggle
  • 79.42 %
  • FSM
  • 94.57 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.000s 18.691us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 2.000s 56.328us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.000s 13.712us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.000s 292.153us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 2.000s 39.315us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.000s 84.252us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.000s 13.712us 1 1 100.00
edn_csr_aliasing 2.000s 39.315us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.000s 58.800us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.000s 58.800us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.000s 58.800us 1 1 100.00
interrupts 1 1 100.00
edn_intr 2.000s 38.273us 1 1 100.00
alerts 1 1 100.00
edn_alert 2.000s 126.636us 1 1 100.00
errs 1 1 100.00
edn_err 2.000s 35.721us 1 1 100.00
disable 2 2 100.00
edn_disable 1.000s 16.084us 1 1 100.00
edn_disable_auto_req_mode 2.000s 91.304us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 11.000s 2071.217us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.000s 26.365us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.000s 30.849us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.000s 115.741us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.000s 115.741us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 2.000s 56.328us 1 1 100.00
edn_csr_rw 1.000s 13.712us 1 1 100.00
edn_csr_aliasing 2.000s 39.315us 1 1 100.00
edn_same_csr_outstanding 2.000s 65.335us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 2.000s 56.328us 1 1 100.00
edn_csr_rw 1.000s 13.712us 1 1 100.00
edn_csr_aliasing 2.000s 39.315us 1 1 100.00
edn_same_csr_outstanding 2.000s 65.335us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 7.000s 1560.349us 1 1 100.00
edn_tl_intg_err 3.000s 57.602us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 2.000s 19.258us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 2.000s 126.636us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.000s 1560.349us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.000s 1560.349us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 7.000s 1560.349us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 7.000s 1560.349us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 2.000s 126.636us 1 1 100.00
edn_sec_cm 7.000s 1560.349us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 2.000s 126.636us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 3.000s 57.602us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 40.000s 2121.356us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
edn_stress_all_with_rand_reset 48143889921898796016392361704714925008374664760940087123654511989577977236781 164
UVM_INFO @ 2121356341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---