Simulation Results: edn/edn1

 
20/07/2026 20:41:39 DVSim: v1.49.12 sha: 54120d8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.52 %
  • code
  • 82.35 %
  • assert
  • 98.44 %
  • func
  • 78.78 %
  • line
  • 98.03 %
  • branch
  • 93.07 %
  • cond
  • 87.92 %
  • toggle
  • 87.29 %
  • FSM
  • 45.45 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.030s 18.374us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.010s 55.634us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.140s 16.521us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 5.680s 637.087us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.370s 21.667us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.960s 29.862us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.140s 16.521us 1 1 100.00
edn_csr_aliasing 1.370s 21.667us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.820s 59.872us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.820s 59.872us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.820s 59.872us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.050s 141.586us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.410s 172.420us 1 1 100.00
errs 1 1 100.00
edn_err 1.150s 29.351us 1 1 100.00
disable 2 2 100.00
edn_disable 0.830s 36.982us 1 1 100.00
edn_disable_auto_req_mode 1.120s 94.182us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.900s 886.881us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.820s 18.482us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.060s 25.540us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.020s 62.871us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.020s 62.871us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.010s 55.634us 1 1 100.00
edn_csr_rw 1.140s 16.521us 1 1 100.00
edn_csr_aliasing 1.370s 21.667us 1 1 100.00
edn_same_csr_outstanding 1.070s 69.677us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.010s 55.634us 1 1 100.00
edn_csr_rw 1.140s 16.521us 1 1 100.00
edn_csr_aliasing 1.370s 21.667us 1 1 100.00
edn_same_csr_outstanding 1.070s 69.677us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.370s 1555.974us 1 1 100.00
edn_tl_intg_err 1.400s 84.018us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.010s 19.741us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.410s 172.420us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.370s 1555.974us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.370s 1555.974us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.370s 1555.974us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.370s 1555.974us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.410s 172.420us 1 1 100.00
edn_sec_cm 3.370s 1555.974us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.410s 172.420us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.400s 84.018us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 11.530s 602.504us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
edn_stress_all_with_rand_reset 47124871556468312064398360872447578761902447753370904212733655653263453301452 119
UVM_INFO @ 602504463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---